Core dynamic retention
In this mode, all core logic and RAMs are in retention and the core domain is inoperable. The core can be entered into this power mode when it is in WFI or WFE mode.
The core dynamic retention can be enabled and disabled separately for WFI and WFE by software running on the core. Separate timeout values can be programmed for entry into this mode from WFI and WFE mode:
- Use the CPUPWRCTLR.WFI_RET_CTRL register bits to program timeout values for entry into core dynamic retention mode from WFI mode.
- Use the CPUPWRCTLR.WFE_RET_CTRL register bits to program timeout values for entry into core dynamic retention mode from WFE mode.
When in dynamic retention and the core is synchronous to the cluster, the clock to the core is automatically gated outside of the domain. However, if the core is running asynchronous to the cluster, the system integrator must gate the clock externally during core dynamic retention. For more information, see the Arm® DynamIQ™ Shared Unit Configuration and Sign-off Guide.
The outputs of the domain must be isolated to prevent buffers without power from propagating unknown values to any operational parts of the system.
When the core is in dynamic retention there is support for Snoop, GIC, and debug access, so the core appears as if it were in WFI or WFE mode. When such an incoming access occurs, it stalls and the On PACTIVE bit is set HIGH. The incoming access proceeds when the domain is returned to On using the P-Channel.
When the incoming access completes, and if the core has not exited WFI or WFE mode, then the On PACTIVE bit is set LOW after the programmed retention timeout. The power controller can then request to reenter the core dynamic retention mode.