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Arm Cortex-A55 Core Technical Reference Manual : About the generic timer

About the generic timer

The Generic Timer can schedule events and trigger interrupts that are based on an incrementing counter value. It generates timer events as active-LOW interrupt outputs and event streams.

The Cortex®-A55 core provides a set of timer registers. The timers are:

  • An EL1 Non-secure physical timer.
  • An EL2 Hypervisor physical timer.
  • An EL3 Secure physical timer.
  • A virtual timer.
  • A Hypervisor virtual timer.

The Cortex-A55 core does not include the system counter. This resides in the SoC. The system counter value is distributed to the core with a 64-bit bus.

For more information on the Generic Timer, see the Arm® DynamIQ™ Shared Unit Technical Reference Manual and the Arm® Architecture Reference Manual Armv8, for Armv8-A architecture profile.