You copied the Doc URL to your clipboard.

Arm Cortex-A55 Core Technical Reference Manual : MPIDR, Multiprocessor Affinity Register

MPIDR, Multiprocessor Affinity Register

The MPIDR provides an additional core identification mechanism for scheduling purposes in a cluster. EDDEVAFF0 is a read-only copy of MPIDR accessible from the external debug interface.

Bit field descriptions

MPIDR is a 32-bit register, and is part of the Identification registers functional group.

This register is Read Only.

Figure B1-60 MPIDR bit assignments


RES1, [31]
RES1.
U, [30]

Indicates a uniprocessor system, as distinct from core 0 in a multiprocessor system. This value is:

0b0Core is part of a multiprocessor system.
RES0, [29:25]
res0Reserved.
MT, [24]

Indicates whether the lowest level of affinity consists of logical cores that are implemented using a multi-threading type approach. This value is:

0b1

Affinity 0 represents threads. However, Cortex®-A55 is not multithreaded and so affinity 0 will always be zero. This allows consistency when in a system with other cores that are multithreaded.

Aff2, [23:16]
Affinity level 2. This level of affinity identifies different clusters within the system. The value in this field is equal to the value present on the CLUSTERIDFAFF2 configuration signal.
Aff1, [15:8]
Affinity level 1. This level of affinity identifies individual cores within the local DynamIQ™ cluster. The value can range from 0x00 for core 0, to 0x07 for core 7.
Aff0, [7:0]
Affinity level 0. The level identifies individual threads within a multi-threaded core. The Cortex-A55 core is single-threaded, so this field has the value 0x00.
Configurations

The MPIDR is:

There is one copy of this register that is used in both Secure and Non-secure states.

Bit fields and details not provided in this description are architecturally defined. See the Arm® Architecture Reference Manual Armv8, for Armv8-A architecture profile.

Was this page helpful? Yes No