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Arm Cortex-A55 Core Technical Reference Manual : ID_AA64PFR0_EL1, AArch64 Processor Feature Register 0, EL1

ID_AA64PFR0_EL1, AArch64 Processor Feature Register 0, EL1

The ID_AA64PFR0_EL1 provides additional information about implemented core features in AArch64.

The optional Advanced SIMD and floating-point support is not included in the base product of the core. Arm requires licensees to have contractual rights to obtain the Advanced SIMD and floating-point support.

Bit field descriptions

ID_AA64PFR0_EL1 is a 64-bit register, and is part of the Identification registers functional group.

This register is Read Only.

Figure B2-45 ID_AA64PFR0_EL1 bit assignments


RES0, [63:32]
RES0Reserved.
RAS, [31:28]

RAS extension version. The possible values are:

0x1Version 1 of the RAS extension is present.
GIC, [27:24]

GIC CPU interface:

0x0GIC CPU interface is disabled, GICCDISABLE is HIGH, or not implemented.
0x1GIC CPU interface is implemented and enabled, GICCDISABLE is LOW.
AdvSIMD, [23:20]

Advanced SIMD. The possible values are:

0x1Advanced SIMD, including Half-precision support, is implemented.
0xFAdvanced SIMD is not implemented.

The FP and AdvSIMD both take the same value, as both must be implemented, or neither.

FP, [19:16]

Floating-point. The possible values are:

0x1Floating-point, including Half-precision support, is implemented.
0xFFloating-point is not implemented.

The FP and AdvSIMD both take the same value, as both must be implemented, or neither.

EL3 handling, [15:12]

EL3 exception handling:

0x2Instructions can be executed at EL3 in AArch64 or AArch32 state.
EL2 handling, [11:8]

EL2 exception handling:

0x2Instructions can be executed at EL3 in AArch64 or AArch32 state.
EL1 handling, [7:4]

EL1 exception handling. The possible values are:

0x2Instructions can be executed at EL3 in AArch64 or AArch32 state.
EL0 handling, [3:0]

EL0 exception handling. The possible values are:

0x2Instructions can be executed at EL0 in AArch64 or AArch32 state.
Configurations

ID_AA64PFR0_EL1 is architecturally mapped to External register EDPFR.

Bit fields and details that are not provided in this description are architecturally defined. See the Arm® Architecture Reference Manual Armv8, for Armv8-A architecture profile.

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