MIDR_EL1, Main ID Register, EL1
The MIDR_EL1 provides identification information for the core, including an implementer code for the device and a device ID number.
Bit field descriptions
MIDR_EL1 is a 32-bit register, and is part of the Identification registers functional group.
This register is Read Only.
Figure B2-70 MIDR_EL1 bit assignments
- Implementer, [31:24]
Indicates the implementer code. This value is:
ASCII character 'A' - implementer is Arm Limited.
- Variant, [23:20]
Indicates the variant number of the core. This is the major revision number x in the rx part of the rxpy description of the product revision status. This value is:
- Architecture, [19:16]
Indicates the architecture code. This value is:
Defined by CPUID scheme.
- PartNum, [15:4]
Indicates the primary part number. This value is:
- Revision, [3:0]
Indicates the minor revision number of the core. This is the minor revision number y in the py part of the rxpy description of the product revision status. This value is:
The MIDR_EL1 is:
- Architecturally mapped to the AArch32 MIDR register. See MIDR, Main ID Register.
- Architecturally mapped to external MIDR_EL1 register.
Bit fields and details not provided in this description are architecturally defined. See the Arm® Architecture Reference Manual Armv8, for Armv8-A architecture profile.