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Arm Cortex-A55 Core Technical Reference Manual : AArch32 debug register summary

AArch32 debug register summary

The following table summarizes the 32-bit and 64-bit debug control registers that are accessible in the AArch32 Execution state from the internal CP14 interface. These registers are accessed by the MCR and MRC instructions in the order of CRn, op2, CRm, Op1 or MCRR and MRRC instructions in the order of CRm, Op1.

For those registers not described in this chapter, see the Arm® Architecture Reference Manual Armv8, for Armv8-A architecture profile. See the Memory-mapped debug register summary for a complete list of registers accessible from the internal memory-mapped interface or the external debug interface.

Table D1-1 AArch32 debug register summary

CRn Op2 CRm Op1 Name Type Reset Description
c0 0 c0 0 DBGDIDR RO 0x3518D000 DBGDIDR, Debug ID Register
c0 0 c1 0 DBGDSCRint RO 0x00030000 Debug Status and Control Register, Internal View
c0 0 c2 0 DBGDCCINT RW 0x00000000 Debug Comms Channel Interrupt Enable Register
c0 0 c5 0 DBGDTRTXint WO - Debug Data Transfer Register, Transmit, Internal View
c0 0 c5 0 DBGDTRRXint RO 0x00000000 Debug Data Transfer Register, Receive, Internal View
c0 0 c6 0 DBGWFARa RW - Watchpoint Fault Address Register, res0
c0 0 c7 0 DBGVCR RW 0x00000000 Debug Vector Catch Register
c0 2 c0 0 DBGDTRRXext RW 0x00000000 Debug Data Transfer Register, Receive, External View
c0 2 c2 0 DBGDSCRext RW 0x00030000 Debug Status and Control Register, External View
c0 2 c3 0 DBGDTRTXext RW 0x00000000 Debug Data Transfer Register, Transmit, External View
c0 2 c6 0 DBGOSECCR RW 0x00000000 Debug OS Lock Exception Catch Control Register
c0 4 c0 0 DBGBVR0 RW XXXXXXXXb Debug Breakpoint Value Register 0
c0 4 c1 0 DBGBVR1 RW XXXXXXXXb Debug Breakpoint Value Register 1
c0 4 c2 0 DBGBVR2 RW XXXXXXXXb Debug Breakpoint Value Register 2
c0 4 c3 0 DBGBVR3 RW XXXXXXXXb Debug Breakpoint Value Register 3
c0 4 c4 0 DBGBVR4 RW XXXXXXXXb Debug Breakpoint Value Register 4
c0 4 c5 0 DBGBVR5 RW XXXXXXXXb Debug Breakpoint Value Register 5
c0 5 c0 0 DBGBCR0 RW 00XXXXXXc

Debug Breakpoint Control Register 0

See DBGBCRn_EL1, Debug Breakpoint Control Registers, EL1.

c0 5 c1 0 DBGBCR1 RW 00XXXXXXc

Debug Breakpoint Control Register 1

See DBGBCRn_EL1, Debug Breakpoint Control Registers, EL1.

c0 5 c2 0 DBGBCR2 RW 00XXXXXXc

Debug Breakpoint Control Register 2

See DBGBCRn_EL1, Debug Breakpoint Control Registers, EL1.

c0 5 c3 0 DBGBCR3 RW 00XXXXXXc

Debug Breakpoint Control Register 3

See DBGBCRn_EL1, Debug Breakpoint Control Registers, EL1.

c0 5 c4 0 DBGBCR4 RW 00XXXXXXd

Debug Breakpoint Control Register 4

See DBGBCRn_EL1, Debug Breakpoint Control Registers, EL1.

c0 5 c5 0 DBGBCR5 RW 00XXXXXXd

Debug Breakpoint Control Register 5

See DBGBCRn_EL1, Debug Breakpoint Control Registers, EL1.

c0 6 c0 0 DBGWVR0 RW XXXXXXXXb Debug Watchpoint Value Register 0
c0 6 c1 0 DBGWVR1 RW XXXXXXXXb Debug Watchpoint Value Register 1
c0 6 c2 0 DBGWVR2 RW XXXXXXXXb Debug Watchpoint Value Register 2
c0 6 c3 0 DBGWVR3 RW XXXXXXXXb Debug Watchpoint Value Register 3
c0 7 c0 0 DBGWCR0 RW XXXXXXXXe

Watchpoint Control Register 0

See DBGWCRn_EL1, Debug Watchpoint Control Registers, EL1.

c0 7 c1 0 DBGWCR1 RW XXXXXXXXe

Watchpoint Control Register 1

See DBGWCRn_EL1, Debug Watchpoint Control Registers, EL1.

c0 7 c2 0 DBGWCR2 RW XXXXXXXXe

Watchpoint Control Register 2

See DBGWCRn_EL1, Debug Watchpoint Control Registers, EL1.

c0 7 c3 0 DBGWCR3 RW XXXXXXXXe

Watchpoint Control Register 3

See DBGWCRn_EL1, Debug Watchpoint Control Registers, EL1.

c1 0 c0 0 DBGDRAR[31:0] RO - Debug ROM Address Register, res0
- - c1 - DBGDRAR[63:0] RO -
c1 1 c4 0 DBGBXVR4 RW XXXXXXXXf Debug Breakpoint Extended Value Register 4
c1 1 c5 0 DBGBXVR5 RW XXXXXXXXf Debug Breakpoint Extended Value Register 5
c1 4 c0 0 DBGOSLAR WO - Debug OS Lock Access Register
c1 4 c1 0 DBGOSLSR RO 0x0000000A Debug OS Lock Status Register
c1 4 c3 0 DBGOSDLR RW 0x00000000 Debug OS Double Lock Register
c1 4 c4 0 DBGPRCR RW g Debug Power/Reset Control Register
c2 2 c0 0 DBGDSAR[31:0] RO - Debug Self Address Register res0
- 0 c2 - DBGDSAR[63:0]h RO -
c7 7 c0 0 DBGDEVID2 RO 0x00000000 Debug Device ID Register 2, res0
c7 7 c1 0 DBGDEVID1 RO 0x00000000

DBGDEVID1, Debug Device ID Register 1

c7 7 c2 0 DBGDEVID RO 0x00110F10

DBGDEVID, Debug Device ID Register

c7 6 c8 0 DBGCLAIMSET RW 0x000000FF Debug Claim Tag Set Register
c7 6 c9 0 DBGCLAIMCLR RW 0x00000000 Debug Claim Tag Clear Register
c7 6 c14 0 DBGAUTHSTATUS RO 0x000000AAi Debug Authentication Status Register
a 

Previously returned information about the address of the instruction that accessed a watchpoint address. This register is now deprecated and is res0.

b 

The actual reset value is {30{1'bx}},2'b0

c 

The actual reset value is 32'b000000000x0x0x0xxx0000xxxxx00xx0.

d 

The actual reset value is 32'b00000000xxxx0x0xxx0000xxxxx00xx0.

e 

The actual reset value is 32'b000xxxxx000x0x0xxxxxxxxxxxxxxxx0.

f 

The actual reset value is 32'hxxxxxxxxx.

g 

The actual reset value is 31'b0000000000000000000000000000,EDPRCR.COREPURQ.

h 

Previously defined the offset from the base address defined in DBGDRAR of the physical base address of the debug registers for the core. This register is now deprecated and res0.

i 

The actual reset value is 24'h000000,1'b1,1'b0,1'b1,1'b0,1'b1,1'b0,1'b1,1'b0.

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