PMCEID0, Performance Monitors Common Event Identification Register 0
The PMCEID0 defines which common architectural and common microarchitectural feature events are implemented.
Bit field descriptions
Figure D4-1 PMCEID0 bit assignments
- ID[31:0], [31:0]
Common architectural and microarchitectural feature events that can be counted by the PMU event counters.
The following table shows the PMCEID0 bit assignments with event implemented or not implemented when the associated bit is set to 1 or 0. See the Arm® Architecture Reference Manual Armv8, for Armv8-A architecture profile for more information about these events.
Table D4-2 PMU events
| Bit | Event number | Event mnemonic | Description | ||||
|---|---|---|---|---|---|---|---|
| [31] | |
L1D_CACHE_ALLOCATE | L1 Data cache allocate:
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| [30] | |
CHAIN | Chain. For odd-numbered counters, counts once for each overflow of the preceding even-numbered counter. For even-numbered counters, does not count:
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| [29] | |
BUS_CYCLES | Bus cycle:
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| [28] | |
TTBR_WRITE_RETIRED | TTBR write, architecturally executed, condition check pass - write to translation table base:
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| [27] | |
INST_SPEC | Instruction speculatively executed:
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| [26] | |
MEMORY_ERROR | Local memory error:
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| [25] | |
BUS_ACCESS | Bus access:
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| [24] | |
L2D_CACHE_WB | L2 Data cache Write-Back:
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| [23] | |
L2D_CACHE_REFILL | L2 Data cache refill:
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| [22] | |
L2D_CACHE | L2 Data cache access:
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| [21] | |
L1D_CACHE_WB | L1 Data cache Write-Back:
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| [20] | |
L1I_CACHE | L1 Instruction cache access:
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| [19] | |
MEM_ACCESS | Data memory access:
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| [18] | |
BR_PRED | Predictable branch speculatively executed:
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| [17] | |
CPU_CYCLES | Cycle:
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| [16] | |
BR_MIS_PRED | Mispredicted or not predicted branch speculatively executed:
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| [15] | |
UNALIGNED_LDST_RETIRED | Instruction architecturally executed, condition check pass - unaligned load or store:
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| [14] | |
BR_RETURN_RETIRED | Instruction architecturally executed, condition check pass - procedure return:
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| [13] | |
BR_IMMED_RETIRED | Instruction architecturally executed - immediate branch:
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| [12] | |
PC_WRITE_RETIRED | Instruction architecturally executed, condition check pass - software change of the PC:
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| [11] | |
CID_WRITE_RETIRED | Instruction architecturally executed, condition check pass - write to CONTEXTIDR:
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| [10] | |
EXC_RETURN | Instruction architecturally executed, condition check pass - exception return:
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| [9] | |
EXC_TAKEN | Exception taken:
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| [8] | |
INST_RETIRED | Instruction architecturally executed:
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| [7] | |
ST_RETIRED | Instruction architecturally executed, condition check pass - store:
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| [6] | |
LD_RETIRED | Instruction architecturally executed, condition check pass - load:
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| [5] | |
L1D_TLB_REFILL | L1 Data TLB refill:
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| [4] | |
L1D_CACHE | L1 Data cache access:
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| [3] | |
L1D_CACHE_REFILL | L1 Data cache refill:
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| [2] | |
L1I_TLB_REFILL | L1 Instruction TLB refill:
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| [1] | |
L1I_CACHE_REFILL | L1 Instruction cache refill:
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| [0] | |
SW_INCR | Instruction architecturally executed, condition check pass - software increment:
|
Bit fields and details not provided in this description are architecturally defined. See the Arm® Architecture Reference Manual Armv8, for Armv8-A architecture profile.