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Arm Cortex-A55 Core Technical Reference Manual : AArch64 Debug register summary

AArch64 Debug register summary

This section summarizes the debug control registers that are accessible in the AArch64 Execution state.

These registers, listed in the following table, are accessed by the MRS and MSR instructions in the order of Op0, CRn, Op1, CRm, Op2.

See Memory-mapped debug register summary for a complete list of registers accessible from the external debug interface. The 64-bit registers cover two addresses on the external memory interface. For those registers not described in this chapter, see the Arm® Architecture Reference Manual Armv8, for Armv8-A architecture profile.

Table D2-1 AArch64 debug register summary

Name Type Reset Width Description
OSDTRRX_EL1 RW 0x00000000 32 Debug Data Transfer Register, Receive, External View
DBGBVR0_EL1 RW - 64 Debug Breakpoint Value Register 0
DBGBCR0_EL1 RW UNK 32 DBGBCRn_EL1, Debug Breakpoint Control Registers, EL1
DBGWVR0_EL1 RW - 64 Debug Watchpoint Value Register 0
DBGWCR0_EL1 RW UNK 32 DBGWCRn_EL1, Debug Watchpoint Control Registers, EL1
DBGBVR1_EL1 RW - 64 Debug Breakpoint Value Register 1
DBGBCR1_EL1 RW UNK 32 DBGBCRn_EL1, Debug Breakpoint Control Registers, EL1
DBGWVR1_EL1 RW - 64 Debug Watchpoint Value Register 1
DBGWCR1_EL1 RW UNK 32 DBGWCRn_EL1, Debug Watchpoint Control Registers, EL1
MDCCINT_EL1 RW 0x00000000 32 Monitor Debug Comms Channel Interrupt Enable Register
MDSCR_EL1 RW - 32 Monitor Debug System Register
DBGBVR2_EL1 RW - 64 Debug Breakpoint Value Register 2
DBGBCR2_EL1 RW UNK 32 DBGBCRn_EL1, Debug Breakpoint Control Registers, EL1
DBGWVR2_EL1 RW - 64 Debug Watchpoint Value Register 2
DBGWCR2_EL1 RW UNK 32 DBGWCRn_EL1, Debug Watchpoint Control Registers, EL1
OSDTRTX_EL1 RW - 32 Debug Data Transfer Register, Transmit, External View
DBGBVR3_EL1 RW - 64 Debug Breakpoint Value Register 3
DBGBCR3_EL1 RW UNK 32 DBGBCRn_EL1, Debug Breakpoint Control Registers, EL1
DBGWVR3_EL1 RW - 64 Debug Watchpoint Value Register 3
DBGWCR3_EL1 RW UNK 32 DBGWCRn_EL1, Debug Watchpoint Control Registers, EL1
DBGBVR4_EL1 RW - 64 Debug Breakpoint Value Register 4
DBGBCR4_EL1 RW UNK 32 DBGBCRn_EL1, Debug Breakpoint Control Registers, EL1
DBGBVR5_EL1 RW - 64 Debug Breakpoint Value Register 5
DBGBCR5_EL1 RW UNK 32 DBGBCRn_EL1, Debug Breakpoint Control Registers, EL1
OSECCR_EL1 RW 0x00000000 32 Debug OS Lock Exception Catch Register
MDCCSR_EL0 RO 0x00000000 32 Monitor Debug Comms Channel Status Register
DBGDTR_EL0 RW 0x00000000 64 Debug Data Transfer Register, half-duplex
DBGDTRTX_EL0 WO 0x00000000 32 Debug Data Transfer Register, Transmit, Internal View
DBGDTRRX_EL0 RO 0x00000000 32 Debug Data Transfer Register, Receive, Internal View
DBGVCR32_EL2 RW - 32 Debug Vector Catch Register
MDRAR_EL1 RO

-

 64 Debug ROM Address Register. This register is reserved, RES0
OSLAR_EL1 WO - 32 Debug OS Lock Access Register
OSLSR_EL1 RO 0x0000000A 32 Debug OS Lock Status Register
OSDLR_EL1 RW 0x00000000 32 Debug OS Double Lock Register
DBGPRCR_EL1 RW - 32 Debug Power/Reset Control Register
DBGCLAIMSET_EL1 RW 0x000000FF 32 Debug Claim Tag Set Register
DBGCLAIMCLR_EL1 RW 0x00000000 32 Debug Claim Tag Clear Register
DBGAUTHSTATUS_EL1 RO 0x000000AA 32 Debug Authentication Status Register
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