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Arm Cortex-A55 Core Technical Reference Manual : PMCEID1_EL0, Performance Monitors Common Event Identification Register 1, EL0

PMCEID1_EL0, Performance Monitors Common Event Identification Register 1, EL0

The PMCEID1_EL0 defines which common architectural and common microarchitectural feature events are implemented.

Bit field descriptions

Figure D5-2 PMCEID1_EL0 bit assignments


ID[63:32], [31:0]

Common architectural and microarchitectural feature events that can be counted by the PMU event counters.

For each bit described in the following table, the event is implemented if the bit is set to 1, or not implemented if the bit is set to 0.

Table D5-3 PMU common events

Bit Event number Event mnemonic Description
[23] 0x37 LL_CACHE_MISS_RD

Last Level cache miss, read.

1This event is implemented.
[22] 0x36 LL_CACHE_RD

Last Level cache access, read.

1This event is implemented.
[21] 0x35 ITLB_WALK

Access to instruction TLB that caused a page table walk.

1This event is implemented.
[20] 0x34 DTLB_WALK

Access to data TLB that caused a page table walk.

1This event is implemented.
[17] 0x31 REMOTE_ACCESS

Access to another socket in a multi-socket system.

1This event is implemented.
[16] 0x30 L2I_TLB

Attributable Level 2 instruction TLB access.

0This event is not implemented.
[15] 0x2F

L2D_TLB

Attributable Level 2 data or unified TLB access.

1This event is implemented.
[14] 0x2E

L2I_TLB_REFILL

Attributable Level 2 instruction TLB refill.

0This event is not implemented.
[13] 0x2D

L2D_TLB_REFILL

Attributable Level 2 data or unified TLB refill.

1This event is implemented.
[12] 0x2C

L3D_CACHE_WB

Attributable Level 3 data or unified cache write-back.

0This event is not implemented.
[11] 0x2B

L3D_CACHE

Attributable Level 3 data or unified cache access.

1This event is implemented if L2 and L3 are present.
0This event is not implemented if L2 and L3 are not present.
[10] 0x2A

L3D_CACHE_REFILL

Attributable Level 3 data or unified cache refill.

1This event is implemented if L2 and L3 are present.
0This event is not implemented if L2 and L3 are not present.
[9] 0x29

L3D_CACHE_ALLOCATE

Attributable Level 3 data or unified cache allocation without refill.

1This event is implemented if L2 and L3 are present.
0This event is not implemented if L2 and L3 are not present.
[8] 0x28

L2I_CACHE_REFILL

Attributable Level 2 instruction cache refill.

0This event is not implemented.
[7] 0x27

L2I_CACHE

Attributable Level 2 instruction cache access.

0This event is not implemented.
[6] 0x26

L1I_TLB

Level 1 instruction TLB access.

1This event is implemented.
[5] 0x25

L1D_TLB

Level 1 data or unified TLB access.

1This event is implemented.
[4] 0x24

STALL_BACKEND

No operation issued due to backend.

1This event is implemented.
[3] 0x23

STALL_FRONTEND

No operation issued due to the frontend.

1This event is implemented.
[2] 0x22

BR_MIS_PRED_RETIRED

Instruction architecturally executed, mispredicted branch.

1This event is implemented.
[1] 0x21

BR_RETIRED

Instruction architecturally executed, branch.

1This event is implemented.
[0] 0x20

L2D_CACHE_ALLOCATE

Level 2 data cache allocation without refill.

1This event is implemented.

Bit fields and details not provided in this description are architecturally defined. See the Arm® Architecture Reference Manual Armv8, for Armv8-A architecture profile.

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