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Arm Cortex-A55 Core Technical Reference Manual : PMCR_EL0, Performance Monitors Control Register, EL0

PMCR_EL0, Performance Monitors Control Register, EL0

The PMCR_EL0 provides details of the Performance Monitors implementation, including the number of counters implemented, and configures and controls the counters.

Bit field descriptions

Figure D5-3 PMCR_EL0 bit assignments


IMP, [31:24]

Implementer code:

0x41Arm.

This is a read-only field.

IDCODE, [23:16]

Identification code:

0x45 Cortex®-A55.

This is a read-only field.

N, [15:11]

Number of event counters.

0b00110Six counters.
RES0, [10:7]
res0Reserved.
LC, [6]

Long cycle count enable. Determines which PMCCNTR_EL0 bit generates an overflow recorded in PMOVSR[31]. The possible values are:

0Overflow on increment that changes PMCCNTR_EL0[31] from 1 to 0.
1Overflow on increment that changes PMCCNTR_EL0[63] from 1 to 0.
DP, [5]

Disable cycle counter, PMCCNTR_EL0 when event counting is prohibited:

0Cycle counter operates regardless of the non-invasive debug authentication settings. This is the reset value.
1Cycle counter is disabled if non-invasive debug is not permitted and enabled.

This bit is read/write.

X, [4]

Export enable. This bit permits events to be exported to another debug device, such as a trace macrocell, over an event bus:

0Export of events is disabled. This is the reset value.
1Export of events is enabled.

This bit is read/write and does not affect the generation of Performance Monitors interrupts on the nPMUIRQ pin.

D, [3]

Clock divider:

0When enabled, PMCCNTR_EL0 counts every clock cycle. This is the reset value.
1When enabled, PMCCNTR_EL0 counts every 64 clock cycles.

This bit is read/write.

C, [2]

Clock counter reset. This bit is WO. The effects of writing to this bit are:

0No action. This is the reset value.
1Reset PMCCNTR_EL0 to 0.

This bit is always RAZ.

Resetting PMCCNTR_EL0 does not clear the PMCCNTR_EL0 overflow bit to 0. See the Arm® Architecture Reference Manual Armv8, for Armv8-A architecture profile for more information.

P, [1]

Event counter reset. This bit is WO. The effects of writing to this bit are:

0No action. This is the reset value.
1Reset all event counters, not including PMCCNTR_EL0, to zero.

This bit is always RAZ.

In Non-secure EL0 and EL1, a write of 1 to this bit does not reset event counters that MDCR_EL2.HPMN reserves for EL2 use.

In EL2 and EL3, a write of 1 to this bit resets all the event counters.

Resetting the event counters does not clear any overflow bits to 0.

E, [0]

Enable. The possible values of this bit are:

0All counters, including PMCCNTR_EL0, are disabled. This is the reset value.
1All counters are enabled.

This bit is RW.

In Non-secure EL0 and EL1, this bit does not affect the operation of event counters that MDCR_EL2.HPMN reserves for EL2 use.

On Warm reset, the field resets to 0.

Configurations

Bit fields and details not provided in this description are architecturally defined. See the Arm® Architecture Reference Manual Armv8, for Armv8-A architecture profile.

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