You copied the Doc URL to your clipboard.

Arm Cortex-A55 Core Technical Reference Manual : ETM register summary

ETM register summary

This section summarizes the ETM trace unit registers.

All ETM trace unit registers are 32-bit wide. The description of each register includes its offset from a base address. The base address is defined by the system integrator when placing the ETM trace unit in the Debug-APB memory map.

The following table lists all of the ETM trace unit registers.

Table D8-1 ETM trace unit register summary

Offset Name Type Reset Description
0x004 TRCPRGCTLR RW 0x00000000 TRCPRGCTLR, Programming Control Register
0x00C TRCSTATR RO 0x00000003 TRCSTATR, Status Register
0x010 TRCCONFIGR RW UNK TRCCONFIGR, Trace Configuration Register
0x018 TRCAUXCTLR RW

0x00000000

TRCAUXCTLR, Auxiliary Control Register
0x020 TRCEVENTCTL0R RW UNK TRCEVENTCTL0R, Event Control 0 Register
0x024 TRCEVENTCTL1R RW UNK TRCEVENTCTL1R, Event Control 1 Register
0x02C TRCSTALLCTLR RW UNK TRCSTALLCTLR, Stall Control Register
0x030 TRCTSCTLR RW UNK TRCTSCTLR, Global Timestamp Control Register
0x034 TRCSYNCPR RW  UNK TRCSYNCPR, Synchronization Period Register
0x038 TRCCCCTLR RW UNK TRCCCCTLR, Cycle Count Control Register
0x03C TRCBBCTLR RW UNK TRCBBCTLR, Branch Broadcast Control Register
0x040 TRCTRACEIDR RW UNK TRCTRACEIDR, Trace ID Register
0x080 TRCVICTLR RW UNK TRCVICTLR, ViewInst Main Control Register
0x084 TRCVIIECTLR RW UNK TRCVIIECTLR, ViewInst Include-Exclude Control Register
0x088 TRCVISSCTLR RW UNK TRCVISSCTLR, ViewInst Start-Stop Control Register
0x100 TRCSEQEVR0 RW UNK TRCSEQEVRn, Sequencer State Transition Control Registers 0-2
0x104 TRCSEQEVR1 RW UNK TRCSEQEVRn, Sequencer State Transition Control Registers 0-2
0x108 TRCSEQEVR2 RW UNK TRCSEQEVRn, Sequencer State Transition Control Registers 0-2
0x118 TRCSEQRSTEVR RW UNK TRCSEQRSTEVR, Sequencer Reset Control Register
0x11C TRCSEQSTR RW UNK TRCSEQSTR, Sequencer State Register
0x120 TRCEXTINSELR RW UNK TRCEXTINSELR, External Input Select Register
0x140 TRCCNTRLDVR0 RW UNK TRCCNTRLDVRn, Counter Reload Value Registers 0-1
0x144 TRCCNTRLDVR1 RW UNK TRCCNTRLDVRn, Counter Reload Value Registers 0-1
0x150 TRCCNTCTLR0 RW UNK TRCCNTCTLR0, Counter Control Register 0
0x154 TRCCNTCTLR1 RW UNK TRCCNTCTLR1, Counter Control Register 1
0x160 TRCCNTVR0 RW UNK TRCCNTVRn, Counter Value Registers 0-1
0x164 TRCCNTVR1 RW UNK TRCCNTVRn, Counter Value Registers 0-1
0x180 TRCIDR8 RO

0x00000000

TRCIDR8, ID Register 8
0x184 TRCIDR9 RO

0x00000000

TRCIDR9, ID Register 9
0x188 TRCIDR10 RO

0x00000000

TRCIDR10, ID Register 10
0x18C TRCIDR11 RO

0x00000000

TRCIDR11, ID Register 11
0x190 TRCIDR12 RO

0x00000000

TRCIDR12, ID Register 12
0x194 TRCIDR13 RO

0x00000000

TRCIDR13, ID Register 13
0x1C0 TRCIMSPEC0 RW

0x00000000

TRCIMSPEC0, Implementation Specific Register 0
0x1E0 TRCIDR0 RO

0x28000EA1

TRCIDR0, ID Register 0
0x1E4 TRCIDR1 RO

0x41001422

TRCIDR1, ID Register 1
0x1E8 TRCIDR2 RO

0x20001048

TRCIDR2, ID Register 2
0x1EC TRCIDR3 RO

0x0D7B0004

TRCIDR3, ID Register 3
0x1F0 TRCIDR4 RO

0x11170004

TRCIDR4, ID Register 4
0x1F4 TRCIDR5 RO

0x2883842F

TRCIDR5, ID Register 5
0x200 TRCRSCTLRn RW UNK TRCRSCTLRn, Resource Selection Control Registers 2-16, n is 2, 15
0x280 TRCSSCCR0 RW UNK TRCSSCCR0, Single-Shot Comparator Control Register 0
0x2A0 TRCSSCSR0 RW UNK TRCSSCSR0, Single-Shot Comparator Status Register 0
0x300 TRCOSLAR WO 0x00000001 TRCOSLAR, OS Lock Access Register
0x304 TRCOSLSR RO 0x0000000A TRCOSLSR, OS Lock Status Register
0x310 TRCPDCR RW 0x00000000 TRCPDCR, Power Down Control Register
0x314 TRCPDSR RO 0x00000013 TRCPDSR, Power Down Status Register
0x400 TRCACVRn RW UNK TRCACVRn, Address Comparator Value Registers 0-7
0x480 TRCACATRn RW UNK TRCACATRn, Address Comparator Access Type Registers 0-7
0x600 TRCCIDCVR0 RW UNK TRCCIDCVR0, Context ID Comparator Value Register 0
0x640 TRCVMIDCVR0 RW UNK TRCVMIDCVR0, VMID Comparator Value Register 0
0x680 TRCCIDCCTLR0 RW UNK TRCCIDCCTLR0, Context ID Comparator Control Register 0
0x688 TRCVMIDCCTRL0 RW UNK Virtual context identifier Comparator Control Register 0
0xEE4 TRCITATBIDR RW UNK TRCITATBIDR, Integration ATB Identification Register
0xEEC TRCITIDATAR WO UNK TRCITIDATAR, Integration Instruction ATB Data Register
0xEF4 TRCITIATBINR RO UNK TRCITIATBINR, Integration Instruction ATB In Register
0xEFC TRCITIATBOUTR WO UNK TRCITIATBOUTR, Integration Instruction ATB Out Register
0xF00 TRCITCTRL RW

0x00000000

TRCITCTRL, Integration Mode Control Register
0xFA0 TRCCLAIMSET RW UNK TRCCLAIMSET, Claim Tag Set Register
0xFA4 TRCCLAIMCLR RW

0x00000000

TRCCLAIMCLR, Claim Tag Clear Register
0xFA8 TRCDEVAFF0 RO UNK TRCDEVAFF0, Device Affinity Register 0
0xFAC TRCDEVAFF1 RO UNK TRCDEVAFF1, Device Affinity Register 1
0xFB0 TRCLAR WO UNK TRCLAR, Software Lock Access Register
0xFB4 TRCLSR RO 0x00000000 TRCLSR, Software Lock Status Register
0xFB8 TRCAUTHSTATUS RO UNK TRCAUTHSTATUS, Authentication Status Register
0xFBC TRCDEVARCH RO 0x47724A13 TRCDEVARCH, Device Architecture Register
0xFC8 TRCDEVID RO

0x00000000

TRCDEVID, Device ID Register
0xFCC TRCDEVTYPE RO 0x00000013 TRCDEVTYPE, Device Type Register
0xFE0 TRCPIDR0 RO

0x0000000A

TRCPIDR0, ETM Peripheral Identification Register 0
0xFE4 TRCPIDR1 RO

0x000000BD

TRCPIDR1, ETM Peripheral Identification Register 1
0xFE8 TRCPIDR2 RO

0x0000002B

TRCPIDR2, ETM Peripheral Identification Register 2
0xFEC TRCPIDR3 RO

0x00000000

TRCPIDR3, ETM Peripheral Identification Register 3
0xFD0 TRCPIDR4 RO

0x00000004

TRCPIDR4, ETM Peripheral Identification Register 4
0xFD4-0xFDC TRCPIDRn RO 0x00000000 TRCPIDRn, ETM Peripheral Identification Registers 5-7
0xFF0 TRCCIDR0 RO

0x0000000D

TRCCIDR0, ETM Component Identification Register 0
0xFF4 TRCCIDR1 RO

0x00000090

TRCCIDR1, ETM Component Identification Register 1
0xFF8 TRCCIDR2 RO

0x00000005

TRCCIDR2, ETM Component Identification Register 2
0xFFC TRCCIDR3 RO

0x000000B1

TRCCIDR3, ETM Component Identification Register 3
Was this page helpful? Yes No