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Arm Cortex-A55 Core Technical Reference Manual : TRCEVENTCTL0R, Event Control 0 Register

TRCEVENTCTL0R, Event Control 0 Register

The TRCEVENTCTL0R controls the tracing of events in the trace stream. The events also drive the external outputs from the ETM trace unit. The events are selected from the Resource Selectors.

Bit field descriptions

Figure D8-24 TRCEVENTCTL0R bit assignments


TYPE3, [31]

Selects the resource type for trace event 3:

0Single selected resource.
1Boolean combined resource pair.
RES0, [30:28]
res0Reserved.
SEL3, [27:24]

Selects the resource number, based on the value of TYPE3:

When TYPE3 is 0, selects a single selected resource from 0-15 defined by bits[3:0].

When TYPE3 is 1, selects a Boolean combined resource pair from 0-7 defined by bits[2:0].

TYPE2, [23]

Selects the resource type for trace event 2:

0Single selected resource.
1Boolean combined resource pair.
RES0, [22:20]
res0Reserved.
SEL2, [19:16]

Selects the resource number, based on the value of TYPE2:

When TYPE2 is 0, selects a single selected resource from 0-15 defined by bits[3:0].

When TYPE2 is 1, selects a Boolean combined resource pair from 0-7 defined by bits[2:0].

TYPE1, [15]

Selects the resource type for trace event 1:

0Single selected resource.
1Boolean combined resource pair.
RES0, [14:12]
res0Reserved.
SEL1, [11:8]

Selects the resource number, based on the value of TYPE1:

When TYPE1 is 0, selects a single selected resource from 0-15 defined by bits[3:0].

When TYPE1 is 1, selects a Boolean combined resource pair from 0-7 defined by bits[2:0].

TYPE0, [7]

Selects the resource type for trace event 0:

0Single selected resource.
1Boolean combined resource pair.
RES0, [6:4]
res0Reserved.
SEL0, [3:0]

Selects the resource number, based on the value of TYPE0:

When TYPE0 is 0, selects a single selected resource from 0-15 defined by bits[3:0].

When TYPE0 is 1, selects a Boolean combined resource pair from 0-7 defined by bits[2:0].

Bit fields and details not provided in this description are architecturally defined. See the Arm® Architecture Reference Manual Armv8, for Armv8-A architecture profile.

The TRCEVENTCTL0R can be accessed through the external debug interface, offset 0x020.

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