TRCIDR3, ID Register 3
The TRCIDR3 indicates:
- Whether TRCVICTLR is supported.
- The number of cores available for tracing.
- If an exception level supports instruction tracing.
- The minimum threshold value for instruction trace cycle counting.
- Whether the synchronization period is fixed.
- Whether TRCSTALLCTLR is supported and if so whether it supports trace overflow prevention and supports stall control of the core.
Bit field descriptions
Figure D8-30 TRCIDR3 bit assignments
- NOOVERFLOW, 
Indicates whether TRCSTALLCTLR.NOOVERFLOW is implemented:
TRCSTALLCTLR.NOOVERFLOW is not implemented.
- NUMPROC, [30:28]
Indicates the number of cores available for tracing:
The trace unit can trace one core, ETM trace unit sharing not supported.
- SYSSTALL, 
Indicates whether stall control is implemented:
The system supports core stall control.
- STALLCTL, 
Indicates whether TRCSTALLCTLR is implemented:
TRCSTALLCTLR is implemented.
This field is used in conjunction with SYSSTALL.
- SYNCPR, 
Indicates whether there is a fixed synchronization period:
TRCSYNCPR is read-write so software can change the synchronization period.
- TRCERR, 
Indicates whether TRCVICTLR.TRCERR is implemented:
TRCVICTLR.TRCERR is implemented.
- EXLEVEL_NS, [23:20]
Each bit controls whether instruction tracing in Non-secure state is implemented for the corresponding Exception level:
Instruction tracing is implemented for Non-secure EL0, EL1, and EL2 Exception levels.
- EXLEVEL_S, [19:16]
Each bit controls whether instruction tracing in Secure state is implemented for the corresponding Exception level:
Instruction tracing is implemented for Secure EL0, EL1, and EL3 Exception levels.
- RES0, [15:12]
- CCITMIN, [11:0]
The minimum value that can be programmed in TRCCCCTLR.THRESHOLD:
Instruction trace cycle counting minimum threshold is 4.
Bit fields and details not provided in this description are architecturally defined. See the Arm® Architecture Reference Manual Armv8, for Armv8-A architecture profile.
The TRCIDR3 can be accessed through the external debug interface, offset