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Arm Cortex-A55 Core Technical Reference Manual : TRCITCTRL, Integration Mode Control Register

TRCITCTRL, Integration Mode Control Register

The TRCITCTRL enables topology detection or integration testing, by putting the ETM trace unit into integration mode.

Bit field descriptions

Figure D8-41 TRCITCTRL bit assignments


RES0, [31:1]
res0Reserved.
IME, [0]

Integration mode enable bit. The possible values are:

0The trace unit is not in integration mode.
1

The trace unit is in integration mode. This mode enables:

  • A debug agent to perform topology detection.
  • SoC test software to perform integration testing.

Bit fields and details not provided in this description are architecturally defined. See the Arm® Architecture Reference Manual Armv8, for Armv8-A architecture profile.

The TRCITCTRL can be accessed through the external debug interface, offset 0xF00.

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