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Arm Cortex-A55 Core Technical Reference Manual : TRCSEQEVRn, Sequencer State Transition Control Registers 0-2

TRCSEQEVRn, Sequencer State Transition Control Registers 0-2

The TRCSEQEVRn defines the sequencer transitions that progress to the next state or backwards to the previous state. The ETM trace unit implements a sequencer state machine with up to four states.

Bit field descriptions

Figure D8-59 TRCSEQEVRn bit assignments


RES0, [31:16]
res0Reserved.
B TYPE, [15]

Selects the resource type to move backwards to this state from the next state:

0Single selected resource.
1Boolean combined resource pair.
RES0, [14:12]
res0Reserved.
B SEL, [11:8]

Selects the resource number, based on the value of B TYPE:

When B TYPE is 0, selects a single selected resource from 0-15 defined by bits[3:0].

When B TYPE is 1, selects a Boolean combined resource pair from 0-7 defined by bits[2:0].

F TYPE, [7]

Selects the resource type to move forwards from this state to the next state:

0Single selected resource.
1Boolean combined resource pair.
RES0, [6:4]
res0Reserved.
F SEL, [3:0]

Selects the resource number, based on the value of F TYPE:

When F TYPE is 0, selects a single selected resource from 0-15 defined by bits[3:0].

When F TYPE is 1, selects a Boolean combined resource pair from 0-7 defined by bits[2:0].

Bit fields and details not provided in this description are architecturally defined. See the Arm® Architecture Reference Manual Armv8, for Armv8-A architecture profile.

The TRCSEQEVRn registers can be accessed through the external debug interface, offsets:

TRCSEQEVR0
0x100.
TRCSEQEVR1
0x104.
TRCSEQEVR2
0x108.
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