TRCSEQSTR, Sequencer State Register
The TRCSEQSTR holds the value of the current state of the sequencer.
Bit field descriptions
Figure D8-61 TRCSEQSTR bit assignments
- RES0, [31:2]
- STATE, [1:0]
Current sequencer state:
Bit fields and details not provided in this description are architecturally defined. See the Arm® Architecture Reference Manual Armv8, for Armv8-A architecture profile.
The TRCSEQSTR can be accessed through the external debug interface, offset