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Arm Cortex-A55 Core Technical Reference Manual : TRCSSCSR0, Single-Shot Comparator Status Register 0

TRCSSCSR0, Single-Shot Comparator Status Register 0

The TRCSSCSR0 indicates the status of the single-shot comparator. TRCSSCSR0 is sensitive to instruction addresses.

Bit field descriptions

Figure D8-63 TRCSSCSR0 bit assignments


STATUS, [31]

Single-shot status. This indicates whether any of the selected comparators have matched:

0Match has not occurred.
1Match has occurred at least once.

When programming the ETM trace unit, if TRCSSCCRn.RST is b0, the STATUS bit must be explicitly written to 0 to enable this single-shot comparator control.

RES0, [30:3]
res0Reserved.
DV, [2]

Data value comparator support:

0Single-shot data value comparisons not supported.
DA, [1]

Data address comparator support:

0Single-shot data address comparisons not supported.
INST, [0]

Instruction address comparator support:

1Single-shot instruction address comparisons supported.

Bit fields and details not provided in this description are architecturally defined. See the Arm® Architecture Reference Manual Armv8, for Armv8-A architecture profile.

The TRCSSCSR0 can be accessed through the external debug interface, offset 0x2A0.

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