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Arm Cortex-A55 Core Technical Reference Manual : EDDFR, External Debug Feature Register

EDDFR, External Debug Feature Register

The EDDFR provides top level information about the debug system in AArch64.

Bit field descriptions

Figure D3-7 EDDFR bit assignments


RES0, [63:32]
res0Reserved.
CTX_CMPs, [31:28]

Number of breakpoints that are context-aware, minus 1. These are the highest numbered breakpoints.

RES0, [27:24]
res0Reserved.
WRPs, [23:20]

Number of watchpoints, minus 1. The value of 0b0000 is reserved.

RES0, [19:16]
res0Reserved.
BRPs, [15:12]

Number of breakpoints, minus 1. The value of 0b0000 is reserved.

PMUVer, [11:8]

Performance Monitors extension version. Indicates whether system register interface to Performance Monitors extension is implemented. Defined values are:

0x0000Performance Monitors extension system registers not implemented.
0x0001Performance Monitors extension system registers implemented, PMUv3.
0x11111Implementation defined form of performance monitors supported, PMUv3 not supported.

All other values are reserved.

TraceVer [7:4]

Trace support. Indicates whether system register interface to a trace macrocell is implemented. Defined values are:

0x0000Trace macrocell system registers not implemented.
0x0001Trace macrocell system registers implemented.

All other values are reserved.

A value of 0x0000 only indicates that no system register interface to a trace macrocell is implemented. A trace macrocell might nevertheless be implemented without a system register interface.

UNKOWN, [3:0]
unknownReserved.

Bit fields and details not provided in this description are architecturally defined. See the Arm® Architecture Reference Manual Armv8, for Armv8-A architecture profile.

EDDFR[31:0] can be accessed through the external debug interface, offset 0xD28.

EDDFR[63:32] can be accessed through the external debug interface, offset 0xD2C.

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