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Arm Cortex-A55 Core Technical Reference Manual : EDPFR, External Debug Processor Feature Register

EDPFR, External Debug Processor Feature Register

The EDPFR provides additional information about implemented PE features in AArch64.

Bit field descriptions

Figure D3-9 EDPFR bit assignments


RES0, [63:28]
res0Reserved.
GIC, [27:24]

System register GIC interface. Defined values are:

0x0No System register interface to the GIC is supported.
0x1

System register interface to the GIC CPU interface is supported.

All other values are reserved.

AdvSIMD, [23:20]

Advanced SIMD. Defined values are:

0x0Advanced SIMD is implemented.
0xFAdvanced SIMD is not implemented.

All other values are reserved.

FP, [19:16]

Floating-point. Defined values are:

0x0Floating-point is implemented.
0xFFloating-point is not implemented.

All other values are reserved.

EL3 handling, [15:12]

EL3 exception handling:

0x2

Instructions can be executed at EL3 in AArch64 or AArch32 state.

EL2 handling, [11:8]

EL2 exception handling:

0x2

Instructions can be executed at EL2 in AArch64 or AArch32 state.

EL1 handling, [7:4]

EL1 exception handling. The possible values are:

0x2

Instructions can be executed at EL1 in AArch64 or AArch32 state.

EL0 handling, [3:0]

EL0 exception handling. The possible values are:

0x2

Instructions can be executed at EL0 in AArch64 or AArch32 state.

Bit fields and details not provided in this description are architecturally defined. See the Arm® Architecture Reference Manual Armv8, for Armv8-A architecture profile.

The EDPFR[31:0] can be accessed through the external debug interface, offset 0xD20.

The EDPFR[63:32] can be accessed through the external debug interface, offset 0xD24.

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