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Arm Cortex-A55 Core Technical Reference Manual : EDRCR, External Debug Reserve Control Register

EDRCR, External Debug Reserve Control Register

The EDRCR is part of the Debug registers functional group. This register is used to allow imprecise entry to Debug state and clear sticky bits in EDSCR.

Bit field descriptions

Figure D3-15 EDRCR bit assignments


RES0, [31:5]
res0Reserved.
CBRRQ, [4]

Allow imprecise entry to Debug state. The actions on writing to this bit are:

0No action.
1Allow imprecise entry to Debug state, for example by canceling pending bus accesses. Setting this bit to 1 allows a debugger to request imprecise entry to Debug state. An External Debug Request debug event must be pending before the debugger sets this bit to 1.
CSPA, [3]

Clear Sticky Pipeline Advance. This bit is used to clear the EDSCR.PipeAdv bit to 0. The actions on writing to this bit are:

0No action.
1Clear the EDSCR.PipeAdv bit to 0.
CSE, [2]

Clear Sticky Error. Used to clear the EDSCR cumulative error bits to 0. The actions on writing to this bit are:

0No action
1Clear the EDSCR.{TXU, RXO, ERR} bits, and, if the core is in Debug state, the EDSCR.ITO bit, to 0.
RES0, [1:0]
res0Reserved.

Bit fields and details not provided in this description are architecturally defined. See the Arm® Architecture Reference Manual Armv8, for Armv8-A architecture profile.

The EDRCR can be accessed through the external debug interface, offset 0x090.

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