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Arm Cortex-A55 Core Technical Reference Manual : PMCFGR, Performance Monitors Configuration Register

PMCFGR, Performance Monitors Configuration Register

The PMCFGR contains PMU specific configuration data.

Bit field descriptions

Figure D6-1 PMCFGR bit assignments


RES0, [31:17]
res0Reserved.
EX, [16]

Export supported. The value is:

1Export is supported. PMCR_EL0.EX is read/write.
CCD, [15]

Cycle counter has pre-scale. The value is:

1PMCR_EL0.D is read/write.
CC, [14]

Dedicated cycle counter supported. The value is:

1Dedicated cycle counter is supported.
Size, [13:8]

Counter size. The value is:

0b11111164-bit counters.
N, [7:0]

Number of event counters. The value is:

0x06Six counters.

Bit fields and details not provided in this description are architecturally defined. See the Arm® Architecture Reference Manual Armv8, for Armv8-A architecture profile.

The PMCFGR can be accessed through the external debug interface, offset 0xE00.

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