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Arm Cortex-A55 Core Technical Reference Manual : PMCIDR3, Performance Monitors Component Identification Register 3

PMCIDR3, Performance Monitors Component Identification Register 3

The PMCIDR3 provides information to identify a Performance Monitor component.

Bit field descriptions

Figure D6-5 PMCIDR3 bit assignments


RES0, [31:8]
res0Reserved.
PRMBL_3, [7:0]
0xB1Preamble byte 3.

Bit fields and details not provided in this description are architecturally defined. See the Arm® Architecture Reference Manual Armv8, for Armv8-A architecture profile.

The PMCIDR3 can be accessed through the external debug interface, offset 0xFFC.

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