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Arm Cortex-A55 Core Technical Reference Manual : PMPIDR3, Performance Monitors Peripheral Identification Register 3

PMPIDR3, Performance Monitors Peripheral Identification Register 3

The PMPIDR3 provides information to identify a Performance Monitor component.

Bit field descriptions

Figure D6-9 PMPIDR3 bit assignments


RES0, [31:8]
res0Reserved.
REVAND, [7:4]
0x0Part minor revision.
CMOD, [3:0]
0x0Customer modified.

Bit fields and details not provided in this description are architecturally defined. See the Arm® Architecture Reference Manual Armv8, for Armv8-A architecture profile.

The PMPIDR3 can be accessed through the external debug interface, offset 0xFEC.

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