PMSSSR, PMU Snapshot Status Register
The PMSSSR holds status information about the captured counters.
Bit field descriptions
The PMSSSR is a 32-bit read-only register.
Figure D7-2 PMSSSR bit assignments
- RES0, [31:1]
- Reserved, RES0.
- NC, 
No capture. This bit indicates whether the PMU counters have been captured. The possible values are:
0 PMU counters are captured. 1 PMU counters are not captured.
If there is a security violation, the core does not capture the event counters. The external monitor is responsible for keeping track of whether it managed to capture the snapshot registers from the core.
This bit does not reflect the status of the captured Program Counter Sample registers.
The core resets this bit to 1 by a Warm reset but MPSSSR.NC is overwritten at the first capture.
- There are no configuration notes.
Any access to PMSSSR returns an error if any of the following occurs:
- The core power domain is off.
- DoubleLockStatus() == TRUE.