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PMU snapshot register summary
The snapshot registers are visible in an implementation defined region of the PMU external debug interface. Each time the debugger sends a snapshot request, information is collected to see how the code is executed in the different cores.
The following table describes the PMU snapshot registers implemented in the core.
Table D7-1 PMU snapshot register summary
| Offset | Name | Type | Width | Description |
|---|---|---|---|---|
0x600 |
PMPCSSR_LO | RO | 32 | PMPCSSR, Snapshot Program Counter Sample Register |
0x604 |
PMPCSSR_HI | RO | 32 | |
0x608 |
PMPCIDSSR | RO | 32 | PMCIDSSR, Snapshot CONTEXTIDR_EL1 Sample Register |
0x60C |
PMPCID2SSR | RO | 32 | PMCID2SSR, Snapshot CONTEXTIDR_EL2 Sample Register |
0x610 |
PMSSSR | RO | 32 | PMSSSR, PMU Snapshot Status Register |
0x614 |
PMOVSSR | RO | 32 | PMOVSSR, PMU Overflow Status Snapshot Register |
0x618 |
PMCCNTSR_LO | RO | 32 | PMCCNTSR, PMU Cycle Counter Snapshot Register |
0x61C |
PMCCNTSR_HI | RO | 32 | |
0x620 + 4×n |
PMEVCNTSRn | RO | 32 | PMEVCNTSRn, PMU Cycle Counter Snapshot Registers 0-5 |
0x6F0 |
PMSSCR | WO | 32 | PMSSCR, PMU Snapshot Capture Register |