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Arm Cortex-A55 Core Technical Reference Manual : Revisions

Revisions

This appendix describes the technical changes between released issues of this book

Table B-1 Issue 0000-00

Change Location Affects

First release

- -

Table B-2 Differences between issue 0000-00 and issue 0001-00

Change Location Affects

Editorial changes

- r0p1

Updated the product revision to r0p1

- r0p1

Minor updates in the components section

Components r0p1

Added a set of timer registers

About the generic timer r0p1

Updated the core dynamic retention mode

Core dynamic retention r0p1

Updated the section regarding configuring MMU accesses

Configuring MMU accesses r0p1

Updated the section regarding external aborts

External aborts r0p1

Updated the section regarding mis-programming contiguous hints

Mis-programming contiguous hints r0p1

Updated the section regarding conflict aborts

Conflict aborts r0p1

Updated the direct access to internal memory

Direct access to internal memory r0p1

Added information on outstanding simultaneous transactions supported

About the L2 memory system r0p1

Updated the support for memory types section

Support for memory types r0p1

Updated the cluster registers tables

AArch32 implementation defined register summary, AArch32 registers by functional group, AArch64 implementation defined register summary, AArch64 registers by functional group r0p1

Updated the ACTLR_EL2 register

ACTLR_EL2, Auxiliary Control Register, EL2 r0p1

Updated the ACTLR_EL3 register

ACTLR_EL3, Auxiliary Control Register, EL3 r0p1

Updated the IFSR32_EL2 register

IFSR32_EL2, Instruction Fault Status Register, EL2 r0p1

Updated the VDISR_EL2 register at EL1 using AArch64

VDISR_EL2 at EL1 using AArch64 r0p1

Updated the ERR0PFGCDNR register

ERR0PFGCDNR, Error Pseudo Fault Generation Count Down Register r0p1

Updated the ERR0PFGCTLR, register

ERR0PFGCTLR, Error Pseudo Fault Generation Control Register r0p1

Updated the PMU events

PMU events r0p1

Table B-3 Differences between issue 0001-00 and issue 0100-00

Change Location Affects

Editorial changes.

- r1p0

Updated the product revision to r1p0.

- r1p0

Updated product name.

- r1p0

Global terminology change from 'processor' to 'core' for the product.

- r1p0

Updated FCM to DSU.

- r1p0

Added ELA address size option.

Implementation options. r1p0

Updated the encoding for the L2 TLB.

Encoding for the L2 TLB. r1p0

Added CPU private registers.

AArch32 implementation defined register summary.

AArch32 registers by functional group.

CPUPCR, CPU Private Control Register.

CPUPMR, CPU Private Mask Register.

CPUPOR, CPU Private Operation Register.

CPUPSELR, CPU Private Selection Register.

AArch64 implementation defined register summary.

AArch64 registers by functional group.

CPUPCR_EL3, CPU Private Control Register, EL3.

CPUPMR_EL3, CPU Private Mask Register, EL3.

CPUPOR_EL3, CPU Private Operation Register, EL3.

CPUPSELR_EL3, CPU Private Selection Register, EL3.

r1p0

Added Dot Product instructions introduced in Arm®v8.4‑A.

Implementation options.

AArch32 architectural system register summary.

AArch32 registers by functional group.

ID_ISAR6, Instruction Set Attribute Register 6.

AArch64 architectural system register summary.

AArch64 registers by functional group.

ID_ISAR6_EL1, AArch32 Instruction Set Attribute Register 6, EL1.

ID_AA64ISAR0_EL1, AArch64 Instruction Set Attribute Register 0, EL1.

r1p0

Updated the CPUECTLR and CPUECTLR_EL1 registers.

CPUECTLR, CPU Extended Control Register.

CPUECTLR_EL1, CPU Extended Control Register, EL1.

r1p0

Updated the Use of R15 by Instruction.

Use of R15 by Instruction. r1p0

Table B-4 Differences between issue 0100-00 and issue 0100-01

Change Location Affects

Updated company name to Arm

- r1p0

Updated the encoding for tag and data in the L1 data cache

Encoding for tag and data in the L1 data cache r1p0

Updated the encoding for tag and data in the L1 instruction cache

Encoding for tag and data in the L1 instruction cache r1p0

Updated the transient hit behavior

Support for memory types r1p0

Updated the descriptions of bit[0] and bit[37] of the CPUECTLR register

CPUECTLR, CPU Extended Control Register r1p0

Updated the traps and enalbles in the ERXPFGCDNR, ERXPFGCTLR, and ERXPFGFR registers

ERXPFGCDNR, Selected Error Pseudo Fault Generation Count Down Register, ERXPFGCTLR, Selected Error Pseudo Fault Generation Control Register, and ERXPFGFR, Selected Pseudo Fault Generation Feature Register r1p0
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