You copied the Doc URL to your clipboard.

Supported standards and specifications

The Cortex®-A55 core implements the Arm®v8‑A architecture and some architecture extensions. It also supports various interconnect, interrupt, timer, debug, and trace architectures.

Table A1-2 Compliance with standards and specifications

Architecture specification or standard Version Notes
Arm architecture

Armv8‑A

  • AArch64 and AArch32 execution states at all Exception levels.
  • A64, A32, and T32 instruction sets.
Arm architecture extensions
  • Armv8.1‑A extensions.
  • Armv8.2‑A extensions.
  • Advanced SIMD and floating-point support.

  • Cryptographic Extension.

  • RAS Extension.
  • Armv8.3‑A LDAPR instructions.
  • Armv8.4‑A dot product instructions.
  • You cannot implement floating-point without Advanced SIMD.
  • You cannot implement the Cryptographic Extension without the Advanced SIMD and floating-point support.
  • The Cortex-A55 core implements the LDAPR instructions introduced in the v8.3 extensions.
  • The Cortex-A55 core optionally implements the SDOT and UDOT instructions introduced in the v8.4 extensions.
Generic Interrupt Controller GICv4 -
PMU PMUv3 -
Debug Armv8‑A With support for the debug features added by the Armv8.2‑A extensions.
CoreSight CoreSightv3 -
Embedded Trace Macrocell ETMv4.2 -

See Additional reading for a list of architectural references.