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Main TLB RAM descriptor fields

The Main TLB RAM is divided into two parts, where one part for storing the tag and the other for storing the data. The following tables list the descriptor fields.

Table A6-9 TLB descriptor fields for Tag RAM

Field Bits Width Description
Valid [0] 1 Indicates that the entry is valid.
NS (walk) [1] 1 The security state of core. Used to compare with the NS state for TLB lookup entry match.
ASID [17:2] 16 Indicates the Address Space Identifier (ASID). This field will be 0 if ASID is not used.
VMID [33:18] 16 Indicates the virtual machine identifier. This field will be 0 if VMID is not used.
Size [36:34] 3

Indicates the combined page size of stage 1 and stage 2.

VMSAv8-32 Short-descriptor translation table format:

0b0004KB
0b01064KB
0b1001MB
0b11016MB

VMSAv8-32 Long-descriptor translation table format or VMSAv8-64 translation table when no 16KB page granule is used:

0b0014KB
0b01164KB
0b1012MB
0b111512MB

VMSAv8-64 translation table when 16KB page granule is used.

The Domain[1] bit (bit[44]) is used together to encode the size information (Domain[1]:Size[2:0]):

0b00014KB
0b001164KB
0b01012MB
0b0111512MB
0b100116KB
0b101132MB
nG [37] 1 Indicates the non-global bit.
AP/HYP [40:38] 3

AArch32: Access permissions from stage1 translation or select hypervisor mode flag.

AArch64: Access permissions from stage 1 translation or select the EL2/EL3 flag.

S2AP [42:41] 2 Indicates the stage2 permission for EL1/EL0. For EL2/EL3, S2AP[1] is for the stage1 access permission and S2AP[0] is for identify EL2 or EL3.
Domain [46:43] 4

Indicates the Domain [3:0] information for VMSA and other control information for LPAE.

S1 Size [49:47] 3 Indicates the page or block size of the stage 1 translation result.
Address Sign bit [50] 1 Indicates the VA sign bit, VA[48].
VA [78:51] 28 Indicates the virtual address.
DBM [79] 1 Indicates the Dirty Bit Modifier (DBM) bit.
Parity [81:80] 2 Indicates the parity bits. If parity is not configured, their bits are absent.

Table A6-10 TLB descriptor fields for Data RAM when PBHA is FALSE

Field Bits Width Description
XS1Usr [0] 1

AArch32: Executable and Readable in stage1 user mode.

AArch64: Executable in stage1 user mode

XS1Non-Usr [1] 1 AArch32 and AArch 64: Executable in stage 1 non-user mode.
XS2Usr [2] 1 AArch32 and AArch 64: Executable in stage 2 user mode.
XS2Non-Usr [3] 1 AArch32 and AArch 64: Executable in stage 2 non-user mode.
Memory type and shareability [11:4] 8 Defines the memory attribute.
S2 Level [13:12] 2 The stage 2 level that gave this translation.
NS (descriptor) [14] 1 The security state allocated to this memory region.
PA [42:15] 28 The physical address.
Parity [43] 1 Parity inclusion is dependant on configuration.

Table A6-11 TLB descriptor fields for Data RAM when PBHA is TRUE

Field Bits Width Description
XS1Usr [0] 1

AArch32: Executable and Readable in stage1 user mode.

AArch64: Executable in stage1 user mode

XS1Non-Usr [1] 1 AArch32 and AArch 64: Executable in stage 1 non-user mode.
XS2Usr [2] 1 AArch32 and AArch 64: Executable in stage 2 user mode.
XS2Non-Usr [3] 1 AArch32 and AArch 64: Executable in stage 2 non-user mode.
Memory type and shareability [11:4] 8 Defines the memory attribute.
PBHA bits [13:12] 2 PBHA bits.
S2 Level [15:14] 2 The stage 2 level that gave this translation.
NS (descriptor) [16] 1 The security state allocated to this memory region.
PA [44:17] 28 The physical address.
Parity [45] 1 Parity inclusion is dependant on configuration.