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TRCITIDATAR, Integration Instruction ATB Data Register

The TRCITIDATAR sets the state of the ATDATAMn output pins shown in the TRCITIDATAR bit assignments table.

Bit field descriptions

The TRCITIDATAR is a 32-bit register.

Figure D8-44 TRCITIDATAR bit assignments

RES0, [31:5]
ATDATAM[31], [4]

Drives the ATDATAM[31] output. a

ATDATAM[23], [3]

Drives the ATDATAM[23] output.a

ATDATAM[15], [2]

Drives the ATDATAM[15] output.a

ATDATAM[7], [1]

Drives the ATDATAM[7] output.a

ATDATAM[0], [0]

Drives the ATDATAM[0] output.a

Bit fields and details not provided in this description are architecturally defined. See the Arm® Architecture Reference Manual Armv8, for Armv8-A architecture profile.

The TRCITIDATAR can be accessed through the external debug interface, offset 0xEEC.

a When a bit is set to 0, the corresponding output pin is LOW. When a bit is set to 1, the corresponding output pin is HIGH. The TRCITIDATAR bit values correspond to the physical state of the output pins.
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