You copied the Doc URL to your clipboard.

TRCPDCR, Power Down Control Register

The TRCPDCR request to the system power controller to keep the ETM trace unit powered up.

Bit field descriptions

The TRCPDCR is a 32-bit register.

Figure D8-50 TRCPDCR bit assignments

RES0, [31:4]
PU, [3]

Powerup request, to request that power to the ETM trace unit and access to the trace registers is maintained:

0Power not requested.
1Power requested.

This bit is reset to 0 on a trace unit reset.

RES0, [2:0]

Bit fields and details not provided in this description are architecturally defined. See the Arm® Architecture Reference Manual Armv8, for Armv8-A architecture profile.

The TRCPDCR can be accessed through the external debug interface, offset 0x310.

Was this page helpful? Yes No