TRCSTALLCTLR, Stall Control Register
The TRCSTALLCTLR enables the ETM trace unit to stall the Cortex®-A55 core if the ETM trace unit FIFO overflows.
Bit field descriptions
The TRCSTALLCTLR is a 32-bit register.
Figure D8-64 TRCSTALLCTLR bit assignments
- RES0, [31:9]
- ISTALL, 
Instruction stall bit. Controls if the trace unit can stall the core when the instruction trace buffer space is less than LEVEL:
The trace unit does not stall the core.
The trace unit can stall the core.
- RES0, [7:4]
- LEVEL, [3:2]
Threshold level field. The field can support 4 monotonic levels from
Zero invasion. This setting has a greater risk of an ETM trace unit FIFO overflow.
Maximum invasion occurs but there is less risk of a FIFO overflow.
- RES0, [1:0]
Bit fields and details not provided in this description are architecturally defined. See the Arm® Architecture Reference Manual Armv8, for Armv8-A architecture profile.
The TRCSTALLCTLR can be accessed through the external debug interface, offset