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AArch32 PMU register summary

The PMU counters and their associated control registers are accessible in the AArch32 Execution state from the internal CP15 system register interface with MCR and MRC instructions for 32-bit registers and MCRR and MRRC for 64-bit registers.

The following table gives a summary of the Cortex®-A55 PMU registers in the AArch32 Execution state. For those registers not described in this chapter, see the Arm® Architecture Reference Manual Armv8, for Armv8-A architecture profile.

Table D4-1 PMU register summary in the AArch32 Execution state

CRn Op1 CRm Op2 Name Type Width Reset Description
c9 0 c12 0 PMCR RW 32

0x41453000

PMCR, Performance Monitors Control Register
c9 0 c12 1 PMCNTENSET RW 32

UNK

Performance Monitors Count Enable Set Register

c9 0 c12 2 PMCNTENCLR RW 32

UNK

Performance Monitors Count Enable Clear Register

c9 0 c12 3 PMOVSR RW 32

UNK

Performance Monitors Overflow Flag Status Register
c9 0 c12 4 PMSWINC WO 32 UNK

Performance Monitors Software Increment Register

c9 0 c12 5 PMSELR RW 32 UNK

Performance Monitors Event Counter Selection Register

c9 0 c12 6 PMCEID0 RO 32

If L2 is present: 0x67FFBFFF. If L3 is present: 0x66FFBBFFF. If L2 and L3 are not present: 0x663FBFFF.

PMCEID0, Performance Monitors Common Event Identification Register 0
c9 0 c12 7 PMCEID1 RO 32

If L2 and L3 are present: 0x00F2AE7F. If L2 or L3 is present: 0x00F2A07F. If L2 and L3 are not present: 0x00F2A07E.

PMCEID1, Performance Monitors Common Event Identification Register 1
c9 0 c14 4 PMCEID2 RO 32

UNK

Reserved

c9 0 c14 5 PMCEID3 RO 32

UNK

Reserved

c9 0 c13 0 PMCCNTR[31:0] RW 32 UNK

Performance Monitors Cycle Count Register

c9 3 c13 0 PMCCNTR[63:0] RW 64 UNK
c9 0 c13 1 PMXEVTYPER RW 32 UNK Performance Monitors Selected Event Type Register
c9 0 c13 2 PMXEVCNTR RW 32 UNK Performance Monitors Selected Event Count Register
c9 0 c14 0 PMUSERENR RW 32 UNK

Performance Monitors User Enable Register

c9 0 c14 1 PMINTENSET RW 32

UNK

Performance Monitors Interrupt Enable Set Register

c9 0 c14 2 PMINTENCLR RW 32

UNK

Performance Monitors Interrupt Enable Clear Register

c9 0 c14 3 PMOVSSET RW 32

UNK

Performance Monitor Overflow Flag Status Set Register
c14 0 c8 0 PMEVCNTR0 RW 32 UNK

Performance Monitor Event Count Registers

c14 0 c8 1 PMEVCNTR1 RW 32 UNK
c14 0 c8 2 PMEVCNTR2 RW 32 UNK
c14 0 c8 3 PMEVCNTR3 RW 32 UNK
c14 0 c8 4 PMEVCNTR4 RW 32 UNK
c14 0 c8 5 PMEVCNTR5 RW 32 UNK
c14 0 c12 0 PMEVTYPER0 RW 32 UNK

Performance Monitors Event Type Registers

c14 0 c12 1 PMEVTYPER1 RW 32 UNK
c14 0 c12 2 PMEVTYPER2 RW 32 UNK
c14 0 c12 3 PMEVTYPER3 RW 32 UNK
c14 0 c12 4 PMEVTYPER4 RW 32 UNK
c14 0 c12 5 PMEVTYPER5 RW 32 UNK
c14 0 c15 7 PMCCFILTR RW 32 UNK

Performance Monitors Cycle Count Filter Register

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