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PMCEID0, Performance Monitors Common Event Identification Register 0

The PMCEID0 defines which common architectural and common microarchitectural feature events are implemented.

Bit field descriptions

Figure D4-1 PMCEID0 bit assignments


ID[31:0], [31:0]

Common architectural and microarchitectural feature events that can be counted by the PMU event counters.

The following table shows the PMCEID0 bit assignments with event implemented or not implemented when the associated bit is set to 1 or 0. See the Arm® Architecture Reference Manual Armv8, for Armv8-A architecture profile for more information about these events.

Table D4-2 PMU events

Bit Event number Event mnemonic Description
[31] 0x1F L1D_CACHE_ALLOCATE

L1 Data cache allocate:

0This event is not implemented.
[30] 0x1E CHAIN

Chain. For odd-numbered counters, counts once for each overflow of the preceding even-numbered counter. For even-numbered counters, does not count:

1This event is implemented.
[29] 0x1D BUS_CYCLES

Bus cycle:

1This event is implemented.
[28] 0x1C TTBR_WRITE_RETIRED

TTBR write, architecturally executed, condition check pass - write to translation table base:

1This event is implemented.
[27] 0x1B INST_SPEC

Instruction speculatively executed:

1This event is implemented.
[26] 0x1A MEMORY_ERROR

Local memory error:

1This event is implemented.
[25] 0x19 BUS_ACCESS

Bus access:

1This event is implemented.
[24] 0x18 L2D_CACHE_WB

L2 Data cache Write-Back:

0This event is not implemented if the Cortex®-A55 core has been configured without an L2 cache.
1This event is implemented if the Cortex-A55 core has been configured with an L2 cache.
[23] 0x17 L2D_CACHE_REFILL

L2 Data cache refill:

0This event is not implemented if the Cortex-A55 core has been configured without an L2 and L3 cache. If configured with only an L3 cache, the L3 event will become an L2 event.
1This event is implemented if the Cortex-A55 core has been configured with an L2 or L3 cache.
[22] 0x16 L2D_CACHE

L2 Data cache access:

0This event is not implemented if the Cortex-A55 core has been configured without an L2 and L3 cache. If configured with only an L3 cache, the L3 event will become an L2 event.
1This event is implemented if the Cortex-A55 core has been configured with an L2 or L3 cache.
[21] 0x15 L1D_CACHE_WB

L1 Data cache Write-Back:

1This event is implemented.
[20] 0x14 L1I_CACHE

L1 Instruction cache access:

1This event is implemented.
[19] 0x13 MEM_ACCESS

Data memory access:

1This event is implemented.
[18] 0x12 BR_PRED

Predictable branch speculatively executed:

1This event is implemented.
[17] 0x11 CPU_CYCLES

Cycle:

1This event is implemented.
[16] 0x10 BR_MIS_PRED

Mispredicted or not predicted branch speculatively executed:

1This event is implemented.
[15] 0x0F UNALIGNED_LDST_RETIRED

Instruction architecturally executed, condition check pass - unaligned load or store:

1This event is implemented.
[14] 0x0E BR_RETURN_RETIRED

Instruction architecturally executed, condition check pass - procedure return:

1This event is implemented.
[13] 0x0D BR_IMMED_RETIRED

Instruction architecturally executed - immediate branch:

1This event is implemented.
[12] 0x0C PC_WRITE_RETIRED

Instruction architecturally executed, condition check pass - software change of the PC:

1This event is implemented.
[11] 0x0B CID_WRITE_RETIRED

Instruction architecturally executed, condition check pass - write to CONTEXTIDR:

1This event is implemented.
[10] 0x0A EXC_RETURN

Instruction architecturally executed, condition check pass - exception return:

1This event is implemented.
[9] 0x09 EXC_TAKEN

Exception taken:

1This event is implemented.
[8] 0x08 INST_RETIRED

Instruction architecturally executed:

1This event is implemented.
[7] 0x07 ST_RETIRED

Instruction architecturally executed, condition check pass - store:

1This event is implemented.
[6] 0x06 LD_RETIRED

Instruction architecturally executed, condition check pass - load:

1This event is implemented.
[5] 0x05 L1D_TLB_REFILL

L1 Data TLB refill:

1This event is implemented.
[4] 0x04 L1D_CACHE

L1 Data cache access:

1This event is implemented.
[3] 0x03 L1D_CACHE_REFILL

L1 Data cache refill:

1This event is implemented.
[2] 0x02 L1I_TLB_REFILL

L1 Instruction TLB refill:

1This event is implemented.
[1] 0x01 L1I_CACHE_REFILL

L1 Instruction cache refill:

1This event is implemented.
[0] 0x00 SW_INCR

Instruction architecturally executed, condition check pass - software increment:

1This event is implemented.

Bit fields and details not provided in this description are architecturally defined. See the Arm® Architecture Reference Manual Armv8, for Armv8-A architecture profile.

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