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PMCR, Performance Monitors Control Register

The PMCR provides details of the Performance Monitors implementation, including the number of counters implemented, and configures and controls the counters.

Bit field descriptions

PMCR is a 32-bit register, and is part of the Performance Monitors registers functional group.

Figure D4-3 PMCR bit assignments


IMP, [31:24]

Indicates the implementer code. The value is:

0x41 ASCII character 'A' - implementer is Arm Limited.
IDCODE, [23:16]

Identification code. The value is:

0x45Cortex®-A55 core.
N, [15:11]

Identifies the number of event counters implemented.

0b00110The core implements six event counters.
RES0, [10:7]
res0Reserved.
LC, [6]

Long cycle count enable. Determines which PMCCNTR bit generates an overflow recorded in PMOVSR[31]. The overflow event is generated on a 32-bit or 64-bit boundary. The possible values are:

0b0Overflow event is generated on a 32-bit boundary, when an increment changes PMCCNTR[31] from 1 to 0. This is the reset value.
0b1Overflow event is generated on a 64-bit boundary, when an increment changes PMCCNTR[63] from 1 to 0.
DP, [5]

Disable cycle counter CCNT when event counting is prohibited. The possible values are:

0b0Cycle counter operates regardless of the non-invasive debug authentication settings. This is the reset value.
0b1Cycle counter is disabled if non-invasive debug is not permitted and enabled.
X, [4]

Export enable. This bit permits events to be exported to another debug device, such as a trace macrocell, over an event bus. The possible values are:

0b0Export of events is disabled. This is the reset value.
0b1Export of events is enabled.

No events are exported when counting is prohibited.

This field does not affect the generation of Performance Monitors overflow interrupt requests or signaling to a cross-trigger interface (CTI) that can be implemented as signals exported from the PE.

When this register has an architecturally defined reset value, if this field is implemented as an RW field, it resets to 0.

D, [3]

Clock divider. The possible values are:

0b0When enabled, counter CCNT counts every clock cycle. This is the reset value.
0b1When enabled, counter CCNT counts once every 64 clock cycles.
C, [2]

Cycle counter reset. This bit is WO. The effects of writing to this bit are:

0b0No action. This is the reset value.
0b1Reset PMCCNTR to zero.

This bit is always RAZ.

Resetting PMCCNTR does not clear the PMCCNTR overflow bit to 0. See the Arm® Architecture Reference Manual Armv8, for Armv8-A architecture profile for more information.

P, [1]

Event counter reset. This bit is WO. The effects of writing to this bit are:

0No action. This is the reset value.
0b1Reset all event counters accessible in the current EL, not including PMCCNTR, to zero.

This bit is always RAZ.

In Non-secure EL0 and EL1, a write of 1 to this bit does not reset event counters that HDCR.HPMN or MDCR_EL2.HPMN reserves for EL2 use.

In EL2 and EL3, a write of 1 to this bit resets all the event counters.

Resetting the event counters does not clear any overflow bits to 0.

E, [0]

Enable. The possible values are:

0b0All counters that are accessible at Non-secure EL1, including PMCCNTR, are disabled. This is the reset value.
0b1When this register has an architecturally defined reset value, this field resets to 0.

This bit is RW.

This bit does not affect the operation of event counters that HDCR.HPMN or MDCR_EL2.HPMN reserves for EL2 use.

When this register has an architecturally defined reset value, this field resets to 0.

Configurations

AArch32 System register PMCR is architecturally mapped to AArch64 System register PMCR_EL0. See PMCR_EL0, Performance Monitors Control Register, EL0.

AArch32 System register PMCR bits [6:0] are architecturally mapped to External register PMCR_EL0[6:0].

There is one instance of this register that is used in both Secure and Non-secure states.

This register is in the Warm reset domain. Some or all RW fields of this register have defined reset values. On a Warm or Cold reset these apply only if the PE resets into an Exception level that is using AArch32. Otherwise, on a Warm or Cold reset RW fields in this register reset to architecturally unknown values.

Bit fields and details not provided in this description are architecturally defined. See the Arm® Architecture Reference Manual Armv8, for Armv8-A architecture profile.

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