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MDSCR_EL1, Monitor Debug System Control Register, EL1

The MDSCR_EL1 main control register for the debug implementation.

Bit field descriptions

MDSCR_EL1 is a 32-bit register, and is part of the Debug registers functional group.

Figure D2-4 MDSCR_EL1 bit assignments


RES0, [31]
res0Reserved.
RXfull, [30]

Used for save/restore of EDSCR.RXfull

  • When OSLSR_EL1.OSLK == 0 (the OS lock is unlocked), this bit is RO, and software must treat it as UNK/SBZP.
  • When OSLSR_EL1.OSLK == 1 (the OS lock is locked), this bit is RW.
TXfull, [29]

Used for save/restore of EDSCR.RXfull

  • When OSLSR_EL1.OSLK == 0 (the OS lock is unlocked), this bit is RO, and software must treat it as UNK/SBZP.
  • When OSLSR_EL1.OSLK == 1 (the OS lock is locked), this bit is RW.
RES0, [28]
res0Reserved.
RXO, [27]

Used for save/restore of EDSCR.RXO.

  • When OSLSR_EL1.OSLK == 0 (the OS lock is unlocked), this bit is RO. Software must treat it as UNKNOWN and use an SBZP policy for writes.
  • When OSLSR_EL1.OSLK == 1 (the OS lock is locked), this bit is RW.
TXU, [26]

Used for save/restore of EDSCR.TXU.

  • When OSLSR_EL1.OSLK == 0 (the OS lock is unlocked), this bit is RO. Software must treat it as UNKNOWN and use an SBZP policy for writes.
  • When OSLSR_EL1.OSLK == 1 (the OS lock is locked), this bit is RW.
RES0, [25:24]
res0Reserved.
INTdis, [23:22]

Used for save/restore of EDSCR.INTdis.

  • When OSLSR_EL1.OSLK == 0 (the OS lock is unlocked), this bit is RO. Software must treat it as UNKNOWN and use an SBZP policy for writes.
  • When OSLSR_EL1.OSLK == 1 (the OS lock is locked), this bit is RW.
TDA, [21]

Used for save/restore of EDSCR.TDA.

  • When OSLSR_EL1.OSLK == 0 (the OS lock is unlocked), this bit is RO. Software must treat it as UNKNOWN and use an SBZP policy for writes.
  • When OSLSR_EL1.OSLK == 1 (the OS lock is locked), this bit is RW.
RES0, [20:19]
res0Reserved.
RAZ/WI, [18:16]

Reserved, RAZ/WI. Hardware must implement this as RAZ/WI. Software must not rely on this property as the behavior of reserved values might change in a future revision of the architecture.

MDE, [15]

Monitor debug events. Enable Breakpoint, Watchpoint, and Vector catch debug exceptions.

0Breakpoint, Watchpoint, and Vector catch debug exceptions disabled.
1Breakpoint, Watchpoint, and Vector catch debug exceptions enabled.

When this register has an architecturally-defined reset value, this field resets to a value that is architecturally UNKNOWN on Warm reset.

HDE, [14]

Used for save/restore of EDSCR.HDE.

  • When OSLSR_EL1.OSLK == 0 (the OS lock is unlocked), this bit is RO. Software must treat it as UNKNOWN and use an SBZP policy for writes.
  • When OSLSR_EL1.OSLK == 1 (the OS lock is locked), this bit is RW.
KDE, [13]

Local (kernel) debug enable. If ELD is using AArch64, enable Software debug events within ELD. Permitted values are:

0Software debug events, other than Software breakpoint instructions, disabled within ELD.
1Software debug events enabled within ELD.

res0 if ELD is using AArch32.

When this register has an architecturally-defined reset value, this field resets to a value that is architecturally UNKNOWN on Warm reset.

TDCC, [12]

Traps EL0 accesses to the DCC registers to EL1, from both Execution states:

0

EL0 using AArch64:

  • EL0 accesses to the MDCCSR_EL0, DBGDTR_EL0, DBGDTRTX_EL0, and DBGDTRRX_EL0 registers are not trapped to EL1.

EL0 using AArch32:

  • EL0 accesses to the DBGDSCRint, DBGDTRRXint, DBGDTRTXint, DBGDIDR, DBGDSAR, and DBGDRAR registers are not trapped to EL1.
1

EL0 using AArch64:

  • EL0 accesses to the MDCCSR_EL0, DBGDTR_EL0, DBGDTRTX_EL0, and DBGDTRRX_EL0 registers are trapped to EL1.

EL0 using AArch32:

  • EL0 accesses to the DBGDSCRint, DBGDTRRXint, DBGDTRTXint, DBGDIDR, DBGDSAR, and DBGDRAR registers are trapped to EL1.

All accesses to these AArch32 registers are trapped, including LDC and STC accesses to DBGDTRTXint and DBGDTRRXint, and MRRC accesses to DBGDSAR and DBGDRAR.

Traps of AArch32 PL0 accesses to the DBGDTRRXint and DBGDTRTXint are ignored in Debug state.

When this register has an architecturally-defined reset value, this field resets to a value that is architecturally UNKNOWN on Warm reset.

RES0, [11:7]
res0Reserved.
ERR, [6]

Used for save/restore of EDSCR.ERR.

  • When OSLSR_EL1.OSLK == 0 (the OS lock is unlocked), this bit is RO. Software must treat it as UNKNOWN and use an SBZP policy for writes.
  • When OSLSR_EL1.OSLK == 1 (the OS lock is locked), this bit is RW.
RES0, [5:1]
res0Reserved.
SS, [0]

Software step control bit. If ELD is using AArch64, enable Software step. Permitted values are:

0Software step is disabled.
1Software step is unabled.

res0 if ELD is using AArch32.

When this register has an architecturally-defined reset value, this field resets to a value that is architecturally UNKNOWN on Warm reset.

Configurations

AArch64 System register MDSCR_EL1 is architecturally mapped to AArch32 System register DBGDSCRext. See Arm® Architecture Reference Manual Armv8, for Armv8-A architecture profile.

This register is in the Warm reset domain. Some or all RW fields of this register have defined reset values. On a Warm or Cold reset these apply only if the PE resets into an Exception level that is using AArch64. Otherwise, on a Warm or Cold reset RW fields in this register reset to architecturally UNKNOWN values.

Bit fields and details not provided in this description are architecturally defined. See the Arm® Architecture Reference Manual Armv8, for Armv8-A architecture profile.

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