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TRCACATRn, Address Comparator Access Type Registers 0-7

The TRCACATRn control the access for the corresponding address comparators.

Bit field descriptions

The TRCACATRn is a 64-bit register.

Figure D8-1 TRCACATRn bit assignments


RES0, [63:16]
res0Reserved.
EXLEVEL_NS, [15:12]

Each bit controls whether a comparison can occur in Non-secure state for the corresponding Exception level. The possible values are:

0The trace unit can perform a comparison, in Non-secure state, for Exception level n.
1The trace unit does not perform a comparison, in Non-secure state, for Exception level n.

The Exception levels are:

Bit[12]Exception level 0.
Bit[13]Exception level 1.
Bit[14]Exception level 2.
Bit[15]Always res0.
EXLEVEL_S, [11:8]

Each bit controls whether a comparison can occur in Secure state for the corresponding Exception level. The possible values are:

0The trace unit can perform a comparison, in Secure state, for Exception level n.
1The trace unit does not perform a comparison, in Secure state, for Exception level n.

The Exception levels are:

Bit[8]Exception level 0.
Bit[9]Exception level 1.
Bit[10]Always res0.
Bit[11]Exception level 3.
RES0, [7:4]
res0Reserved.
CONTEXT TYPE, [3:2]

Controls whether the trace unit performs a Context ID comparison, a VMID comparison, or both comparisons:

0b00The trace unit does not perform a Context ID comparison.
0b01The trace unit performs a Context ID comparison using the Context ID comparator that the CONTEXT field specifies, and signals a match if both the Context ID comparator matches and the address comparator match.
0b10The trace unit performs a VMID comparison using the VMID comparator that the CONTEXT field specifies, and signals a match if both the VMID comparator and the address comparator match.
0b11The trace unit performs a Context ID comparison and a VMID comparison using the comparators that the CONTEXT field specifies, and signals a match if the Context ID comparator matches, the VMID comparator matches, and the address comparator matches.
TYPE, [1:0]

Type of comparison:

0b00Instruction address, res0.

Bit fields and details not provided in this description are architecturally defined. See the Arm® Architecture Reference Manual Armv8, for Armv8-A architecture profile.

The TRCACATRn can be accessed through the external debug interface, offset 0x480-0x4B8.

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