You copied the Doc URL to your clipboard.

TRCAUXCTLR, Auxiliary Control Register

The TRCAUXCTLR provides implementation defined configuration and control options.

Bit field descriptions

The TRCAUXCTLR is a 32-bit register.

Figure D8-4 TRCAUXCTLR bit assignments


RES0, [31:8]
res0Reserved.
COREIFEN, [7]

Keep core interface enabled regardless of trace enable register state. The possible values are:

0Core interface enabled is set by trace enable register state.
1Enable core interface, regardless of trace enable register state.
RES0, [6]
res0Reserved.
AUTHNOFLUSH, [5]

Do not flush trace on de-assertion of authentication inputs. The possible values are:

0ETM trace unit FIFO is flushed and ETM trace unit enters idle state when DBGEN or NIDEN is LOW.
1ETM trace unit FIFO is not flushed and ETM trace unit does not enter idle state when DBGEN or NIDEN is LOW.

When this bit is set to 1, the trace unit behavior deviates from architecturally-specified behavior.

TSNODELAY, [4]

Do not delay timestamp insertion based on FIFO depth. The possible values are:

0Timestamp packets are inserted into FIFO only when trace activity is LOW.
1Timestamp packets are inserted into FIFO irrespective of trace activity.
SYNCDELAY, [3]

Delay periodic synchronization if FIFO is more than half-full. The possible values are:

0SYNC packets are inserted into FIFO only when trace activity is low.
1SYNC packets are inserted into FIFO irrespective of trace activity.
OVFLW, [2]

Force overflow if synchronization is not completed when second synchronization becomes due. The possible values are:

0No FIFO overflow when SYNC packets are delayed.
1Forces FIFO overflow when SYNC packets are delayed.

When this bit is set to 1, the trace unit behavior deviates from architecturally-specified behavior.

IDLEACK, [1]

Force idle-drain acknowledge high, CPU does not wait for trace to drain before entering WFX state. The possible values are:

0ETM trace unit idle acknowledge is asserted only when the ETM trace unit is in idle state.
1ETM trace unit idle acknowledge is asserted irrespective of the ETM trace unit idle state.

When this bit is set to 1, trace unit behavior deviates from architecturally-specified behavior.

AFREADY, [0]

Always respond to AFREADY immediately. Does not have any interaction with FIFO draining, even in WFI state. The possible values are:

0ETM trace unit AFREADYM output is asserted only when the ETM trace unit is in idle state or when all the trace bytes in FIFO before a flush request are output.
1ETM trace unit AFREADYM output is always asserted HIGH. When this bit is set to 1, trace unit behavior deviates from architecturally-specified behavior.

Bit fields and details not provided in this description are architecturally defined. See the Arm® Architecture Reference Manual Armv8, for Armv8-A architecture profile.

The TRCAUXCTLR can be accessed through the external debug interface, offset 0x018.

Was this page helpful? Yes No