TRCDEVAFF0, Device Affinity Register 0
The TRCDEVAFF0 provides an additional core identification mechanism for scheduling purposes in a cluster. TRCDEVAFF0 is a read-only copy of MPIDR accessible from the external debug interface.
Bit field descriptions
The TRCDEVAFF0 is a 32-bit register.
Figure D8-20 TRCDEVAFF0 bit assignments
- RES1, 
- U, 
Indicates a single core system, as distinct from core 0 in a cluster. This value is:
Core is part of a multiprocessor system. This is the value for implementations with more than one core, and for implementations with an ACE or CHI master interface.
Core is part of a uniprocessor system. This is the value for single core implementations with an AXI master interface.
- RES0, [29:25]
- MT, 
Indicates whether the lowest level of affinity consists of logical cores that are implemented using a multithreading type approach. This value is:
Performance of cores at the lowest affinity level is largely independent.
- Aff2, [23:16]
Affinity level 2. Second highest level affinity field.
Indicates the value read in the CLUSTERIDAFF2 configuration signal.
- Aff1, [15:8]
Affinity level 1. Third highest level affinity field.
Indicates the value read in the CLUSTERIDAFF1 configuration signal.
- Aff0, [7:0]
Affinity level 0. Lowest level affinity field.
Indicates the core number in the Cortex®-A55 core. The possible values are:
A cluster with one core only.
A cluster with two cores.
A cluster with three cores.
A cluster with four cores.
Bit fields and details not provided in this description are architecturally defined. See the Arm® Architecture Reference Manual Armv8, for Armv8-A architecture profile.
The TRCDEVAFF0 can be accessed through the external debug interface,