TRCIDR0, ID Register 0
The TRCIDR0 returns the tracing capabilities of the ETM trace unit.
Bit field descriptions
The TRCIDR0 is a 32-bit register.
Figure D8-27 TRCIDR0 bit assignments
- RES0, [31:30]
- COMMOPT, 
Indicates the meaning of the commit field in some packets:
Commit mode 1.
- TSSIZE, [28:24]
Global timestamp size field:
Implementation supports a maximum global timestamp of 64 bits.
- RES0, [23:17]
- QSUPP, [16:15]
Indicates Q element support:
Q elements not supported.
- QFILT, 
Indicates Q element filtering support:
Q element filtering not supported.
- CONDTYPE, [13:12]
Indicates how conditional results are traced:
Conditional trace not supported.
- NUMEVENT, [11:10]
Number of events supported in the trace, minus 1:
Four events supported.
- RETSTACK, 
Return stack support:
Return stack implemented.
- RES0, 
- TRCCCI, 
Support for cycle counting in the instruction trace:
Cycle counting in the instruction trace is implemented.
- TRCCOND, 
Support for conditional instruction tracing:
Conditional instruction tracing is not supported.
- TRCBB, 
Support for branch broadcast tracing:
Branch broadcast tracing is implemented.
- TRCDATA, [4:3]
Conditional tracing field:
Tracing of data addresses and data values is not implemented.
- INSTP0, [2:1]
P0 tracing support field:
Tracing of load and store instructions as P0 elements is not supported.
- RES1, 
Bit fields and details not provided in this description are architecturally defined. See the Arm® Architecture Reference Manual Armv8, for Armv8-A architecture profile.
The TRCIDR0 can be accessed through the external debug interface, offset