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TRCPDSR, Power Down Status Register

The TRCPDSR indicates the power down status of the ETM trace unit.

Bit field descriptions

The TRCPDSR is a 32-bit register.

Figure D8-51 TRCPDSR bit assignments


RES0, [31:6]
res0Reserved.
OSLK, [5]

OS lock status.

0The OS Lock is unlocked.
1The OS Lock is locked.
RES0, [4:2]
res0Reserved.
STICKYPD, [1]

Sticky power down state.

0Trace register power has not been removed since the TRCPDSR was last read.
1Trace register power has been removed since the TRCPDSR was last read.

This bit is set to 1 when power to the ETM trace unit registers is removed, to indicate that programming state has been lost. It is cleared after a read of the TRCPDSR.

POWER, [0]

Indicates the ETM trace unit is powered:

0ETM trace unit is not powered. The trace registers are not accessible and they all return an error response.
1ETM trace unit is powered. All registers are accessible.

If a system implementation allows the ETM trace unit to be powered off independently of the debug power domain, the system must handle accesses to the ETM trace unit appropriately.

Bit fields and details not provided in this description are architecturally defined. See the Arm® Architecture Reference Manual Armv8, for Armv8-A architecture profile.

The TRCPDSR can be accessed through the external debug interface, offset 0x314.

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