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TRCSEQSTR, Sequencer State Register

The TRCSEQSTR holds the value of the current state of the sequencer.

Bit field descriptions

The TRCSEQSTR is a 32-bit register

Figure D8-61 TRCSEQSTR bit assignments


RES0, [31:2]
res0Reserved.
STATE, [1:0]

Current sequencer state:

0b00State 0.
0b01State 1.
0b10State 2.
0b11State 3.

Bit fields and details not provided in this description are architecturally defined. See the Arm® Architecture Reference Manual Armv8, for Armv8-A architecture profile.

The TRCSEQSTR can be accessed through the external debug interface, offset 0x11C.

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