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FPEXC, Floating-Point Exception Control register

The FPEXC provides a global enable for the Advanced SIMD and floating-point support, and indicates how the state of this support is recorded.

Bit field descriptions

FPEXC is a 32-bit register.

Figure 3-6 FPEXC bit assignments


EX, [31]

Exception bit. The Cortex®-A55 core implementation does not generate asynchronous floating-point exceptions, therefore this bit is res0.

EN, [30]

Global enable for the Advanced SIMD and floating-point support:

0The Advanced SIMD and floating-point support is disabled. This is the reset value.
1The Advanced SIMD and floating-point support is enabled and operates normally.

It applies only to AArch32 executions, and only when EL1 is not AArch64.

[29:11]
res0Reserved.
[10:8]
res1Reserved.
[7:0]
res0Reserved.
Configurations

FPEXC is architecturally mapped to AArch64 register FPEXC32_EL2. See  FPEXC32_EL2, Floating-point Exception Control Register, EL2.

There is one copy of this register that is used in both Secure and Non-secure states.

Usage constraints

Accessing the FPEXC

To access the FPEXC register:

VMRS <Rt>, FPEXC ; Read FPEXC into Rt

Register access is encoded as follows:

Table 3-8 FPEXC access encoding

spec_reg
1000
Accessibility
This register is accessible as follows:

EL0

(NS)

EL0

(S)

EL1

(NS)

EL1

(S)

EL2

EL3

(SCR.NS = 1)

EL3

(SCR.NS = 0)

- - Config RW Config Config RW

Access to this register depends on the values of CPACR.{cp10,cp11}, NSACR.{cp10,cp11}, and HCPTR.{TCP10,TCP11}. For details of which values of these fields allow access at which Exception levels, see the Arm® Architecture Reference Manual Armv8, for Armv8-A architecture profile.

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