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FPSID, Floating-Point System ID Register

The FPSID provides top-level information about the floating-point implementation.

Bit field descriptions

FPSID is a 32-bit register.

Figure 3-1 FPSID bit assignments


Implementer, [31:24]

Indicates the implementer:

0x41Arm Limited
SW, [23]

Software bit. This bit indicates that a system provides only software emulation of the floating-point instructions:

0The system includes hardware support for floating-point operations.
Subarchitecture, [22:16]

Subarchitecture version number:

0x03VFPv3 architecture, or later, with no subarchitecture. The entire floating-point implementation is in hardware, and requires no software support code. The MVFR0, MVFR1, and MVFR2 registers indicate the VFP architecture version.
Part number, [15:8]

Indicates the part number for the floating-point implementation:

0x40v8-A profile.
Variant, [7:4]

Indicates the variant number:

5Cortex®-A55 core.
Revision, [3:0]

Indicates the revision number for the floating-point implementation:

2r1p0.
Configurations

Access to this register depends on the values of CPACR.{cp10,cp11}, NSACR.{cp10,cp11}, and HCPTR.{TCP10,TCP11}. For details of which field values permit access at specific Exception levels, see the Arm® Architecture Reference Manual Armv8, for Armv8-A architecture profile.

This register largely duplicates information that is held in the MIDR. Arm deprecates use of it.

Usage constraints

Accessing the FPSID

To access the FPSID:

VMRS <Rt>, FPSID ; Read FPSID into Rt

Register access is encoded as follows:

Table 3-3 FPSID access encoding

spec_reg
0000
Accessibility
This register is accessible as follows:

EL0

(NS)

EL0

(S)

EL1

(NS)

EL1

(S)

EL2

EL3

(SCR.NS = 1)

EL3

(SCR.NS = 0)

- - Config RO Config Config RO
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