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MVFR0, Media and VFP Feature Register 0

The MVFR0 describes the features provided by the AArch32 Advanced SIMD and floating-point implementation.

Bit field descriptions

MVFR0 is a 32-bit register.

Figure 3-3 MVFR0 bit assignments


FPRound, [31:28]

Indicates the rounding modes supported by the floating-point hardware:

0x1All rounding modes supported.
FPShVec, [27:24]

Indicates the hardware support for floating-point short vectors:

0x0Not supported.
FPSqrt, [23:20]

Indicates the hardware support for floating-point square root operations:

0x1Supported.
FPDivide, [19:16]

Indicates the hardware support for floating-point divide operations:

0x1Supported.
FPTrap, [15:12]

Indicates whether the floating-point hardware implementation supports exception trapping:

0x0Not supported.
FPDP, [11:8]

Indicates the hardware support for floating-point double-precision operations:

0x2Supported, VFPv3, or greater.

See the Arm® Architecture Reference Manual Armv8, for Armv8-A architecture profile for more information.

FPSP, [7:4]

Indicates the hardware support for floating-point single-precision operations:

0x2Supported, VFPv3, or greater.

See the Arm® Architecture Reference Manual Armv8, for Armv8-A architecture profile for more information.

SIMDReg, [3:0]

Indicates support for the Advanced SIMD register bank:

0x2Supported, 32 x 64-bit registers supported.

See the Arm® Architecture Reference Manual Armv8, for Armv8-A architecture profile for more information.

Configurations

MVFR0 is architecturally mapped to AArch64 register MVFR0_EL1. See  MVFR0_EL1, Media and VFP Feature Register 0, EL1.

There is one copy of this register that is used in both Secure and Non-secure states.

Usage constraints

Accessing the MVFR0

To access the MVFR0:

VMRS <Rt>, MVFR0 ; Read MVFR0 into Rt

Register access is encoded as follows:

Table 3-5 MVFR0 access encoding

spec_reg
0111
Accessibility
This register is accessible as follows:

EL0

(NS)

EL0

(S)

EL1

(NS)

EL1

(S)

EL2

EL3

(SCR.NS = 1)

EL3

(SCR.NS = 0)

- - Config RO Config Config RO

Access to this register depends on the values of CPACR.{cp10,cp11}, NSACR.{cp10,cp11}, HCPTR.{TCP10,TCP11}, and FPEXC.EN. For details of which values of these fields allow access at which Exception levels, see the Arm® Architecture Reference Manual Armv8, for Armv8-A architecture profile.

MVFR0 must be interpreted with MVFR1 and MVFR2. See  MVFR1, Media and VFP Feature Register 1 and   MVFR2, Media and VFP Feature Register 2.

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