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MVFR1, Media and VFP Feature Register 1

The MVFR1 describes the features provided by the AArch32 Advanced SIMD and floating-point implementation.

Bit field descriptions

MVFR1 is a 32-bit register.

Figure 3-4 MVFR1 bit assignments


SIMDFMAC, [31:28]

Indicates whether the Advanced SIMD and floating-point unit supports fused multiply accumulate operations:

0x1Implemented.
FPHP, [27:24]

Indicates whether the Advanced SIMD and floating-point unit supports half-precision floating-point conversion instructions:

0x3Floating-point half precision conversion and data processing instructions implemented.
SIMDHP, [23:20]

Indicates whether the Advanced SIMD and floating-point unit supports half-precision floating-point conversion operations:

0x2Advanced SIMD precision conversion and data processing instructions implemented.
SIMDSP, [19:16]

Indicates whether the Advanced SIMD and floating-point unit supports single-precision floating-point operations:

0x1Implemented.
SIMDInt, [15:12]

Indicates whether the Advanced SIMD and floating-point unit supports integer operations:

0x1Implemented.
SIMDLS, [11:8]

Indicates whether the Advanced SIMD and floating-point unit supports load/store instructions:

0x1Implemented.
FPDNaN, [7:4]

Indicates whether the floating-point hardware implementation supports only the Default NaN mode:

0x1Hardware supports propagation of NaN values.
FPFtZ, [3:0]

Indicates whether the floating-point hardware implementation supports only the Flush-to-zero mode of operation:

0x1Hardware supports full denormalized number arithmetic.
Configurations

MVFR1 is architecturally mapped to AArch64 register MVFR1_EL1. See  MVFR1_EL1, Media and VFP Feature Register 1, EL1.

There is one copy of this register that is used in both Secure and Non-secure states.

Usage constraints

Accessing the MVFR1

To access the MVFR1:

VMRS <Rt>, MVFR1 ; Read MVFR1 into Rt

Register access is encoded as follows:

Table 3-6 MVFR1 access encoding

spec_reg
0110
Accessibility
This register is accessible as follows:

EL0

(NS)

EL0

(S)

EL1

(NS)

EL1

(S)

EL2

EL3

(SCR.NS = 1)

EL3

(SCR.NS = 0)

- - Config RO Config Config RO

Access to this register depends on the values of CPACR.{cp10,cp11}, NSACR.{cp10,cp11}, HCPTR.{TCP10,TCP11}, and FPEXC.EN. For details of which values of these fields allow access at which Exception levels, see the Arm® Architecture Reference Manual Armv8, for Armv8-A architecture profile.

MVFR1 must be interpreted with MVFR0 and MVFR2. See  MVFR0, Media and VFP Feature Register 0 and   MVFR2, Media and VFP Feature Register 2.

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