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MVFR0_EL1, Media and VFP Feature Register 0, EL1

The MVFR0_EL1 describes the features provided by the AArch64 Advanced SIMD and floating-point implementation.

Bit field descriptions

MVFR0_EL1 is a 32-bit register.

Figure 2-3 MVFR0_EL1 bit assignments


FPRound, [31:28]

Indicates the rounding modes supported by the floating-point hardware:

0x1All rounding modes supported.
FPShVec, [27:24]

Indicates the hardware support for floating-point short vectors:

0x0Not supported.
FPSqrt, [23:20]

Indicates the hardware support for floating-point square root operations:

0x1Supported.
FPDivide, [19:16]

Indicates the hardware support for floating-point divide operations:

0x1Supported.
FPTrap, [15:12]

Indicates whether the floating-point hardware implementation supports exception trapping:

0x0Not supported.
FPDP, [11:8]

Indicates the hardware support for floating-point double-precision operations:

0x2Supported, VFPv3 or greater.

See the Arm® Architecture Reference Manual Armv8, for Armv8-A architecture profile for more information.

FPSP, [7:4]

Indicates the hardware support for floating-point single-precision operations:

0x2Supported, VFPv3 or greater.

See the Arm® Architecture Reference Manual Armv8, for Armv8-A architecture profile for more information.

SIMDReg, [3:0]

Indicates support for the Advanced SIMD register bank:

0x2Supported, 32 x 64-bit registers supported.

See the Arm® Architecture Reference Manual Armv8, for Armv8-A architecture profile for more information.

Configurations
MVFR0_EL1 is architecturally mapped to AArch32 register MVFR0. See  MVFR0, Media and VFP Feature Register 0.

Usage constraints

Accessing the MVFR0_EL1

To access the MVFR0_EL1:

MRS <Xt>, MVFR0_EL1 ; Read MVFR0_EL1 into Xt

Register access is encoded as follows:

Table 2-5 MVFR0_EL1 access encoding

op0 op1 CRn CRm op2
11 000 0000 0011 000
Accessibility
This register is accessible as follows:
EL0 EL1(NS) EL1(S) EL2 EL3 (SCR.NS = 1) EL3(SCR.NS = 0)
- RO RO RO RO RO
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