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MVFR1_EL1, Media and VFP Feature Register 1, EL1

The MVFR1_EL1 describes the features provided by the AArch64 Advanced SIMD and floating-point implementation.

Bit field descriptions

MVFR1_EL1 is a 32-bit register.

Figure 2-4 MVFR1_EL1 bit assignments


SIMDFMAC, [31:28]

Indicates whether the Advanced SIMD and floating-point unit supports fused multiply accumulate operations:

1Implemented.
FPHP, [27:24]

Indicates whether the Advanced SIMD and floating-point unit supports half-precision floating-point conversion instructions:

3Floating-point half precision conversion and data processing instructions implemented.
SIMDHP, [23:20]

Indicates whether the Advanced SIMD and floating-point unit supports half-precision floating-point conversion operations:

2Advanced SIMD half precision conversion and data processing instructions implemented.
SIMDSP, [19:16]

Indicates whether the Advanced SIMD and floating-point unit supports single-precision floating-point operations:

1Implemented.
SIMDInt, [15:12]

Indicates whether the Advanced SIMD and floating-point unit supports integer operations:

1Implemented.
SIMDLS, [11:8]

Indicates whether the Advanced SIMD and floating-point unit supports load/store instructions:

1Implemented.
FPDNaN, [7:4]

Indicates whether the floating-point hardware implementation supports only the Default NaN mode:

1Hardware supports propagation of NaN values.
FPFtZ, [3:0]

Indicates whether the floating-point hardware implementation supports only the Flush-to-zero mode of operation:

1Hardware supports full denormalized number arithmetic.
Configurations
MVFR1_EL1 is architecturally mapped to AArch32 register MVFR1. See  MVFR1, Media and VFP Feature Register 1.

Usage constraints

Accessing the MVFR1_EL1

To access the MVFR1_EL1:

MRS <Xt>, MVFR1_EL1 ; Read MVFR1_EL1 into Xt

Register access is encoded as follows:

Table 2-6 MVFR1_EL1 access encoding

op0 op1 CRn CRm op2
11 000 0000 0011 001
Accessibility
This register is accessible as follows:
EL0 EL1(NS) EL1(S) EL2 EL3 (SCR.NS = 1) EL3(SCR.NS = 0)
- RO RO RO RO RO
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