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About the Advanced SIMD and floating-point support

The Cortex-A55 floating-point implementation:

  • Does not generate floating-point exceptions.
  • Implements all scalar operations in hardware with support for all combinations of:

    • Rounding modes.

    • Flush-to-zero.
    • Default Not a Number (NaN) modes.

The Arm®v8‑A architecture does not define a separate version number for its Advanced SIMD and floating-point support in the AArch64 execution state because the instructions are always implicitly present.

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