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Functional Description

Table of Contents

Introduction
About the DSU
Features
Implementation options
Cluster configurations
Supported standards and specifications
Test features
Design tasks
Product revisions
Technical overview
Components
Interfaces
RAS support
Page-based hardware attributes
L3 memory system variants
Clocks and resets
Clocks
Resets
Power management
About DSU power management
Power mode control
Communication with the power controller
L3 RAM power control
L3 cache partial powerdown
L3 RAM retention
Power modes
Power mode transitions
Power mode transition behavior
Interlocks between core and DSU P-Channels
Power mode encoding
Power operating requirements
Power control for DFT
Wait For Interrupt and Wait For Event
Clock, voltage, and power domains
Cluster powerdown
Transitioning in and out of coherency
L3 cache
About the L3 cache
L3 cache allocation policy
L3 cache partitioning
Cache stashing
L3 cache ECC and parity
L3 cache data RAM latency
Cache slices and portions
Cache slice and master port selection
Default number of cache slices
Implementing a 1.5MB or 3MB L3 cache
ACE master interface
About the ACE master interface
Dual ACE interfaces
ACE configurations
ACE features
ACE master interface attributes
ACE channel properties
ACE transactions
Support for memory types
Read response
Write response
Barriers
AXI compatibility mode
Additional logic to support AXI compatibility
ACE privilege information
CHI master interface
About the CHI master interface
Dual CHI interfaces
CHI version
CHI features
CHI configurations
Attributes of the CHI master interface
CHI channel properties
CHI transactions
Use of DataSource
Support for memory types
ACP slave interface
About the ACP
ACP features
ACP ACE5-Lite subset
ACP transaction types
ACP performance
AXI master peripheral port
About the peripheral port
Transaction ID encoding
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