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A.1 Clock and clock control signals

List of clock and clock control signals.

Table A-1 Cortex-A9 MPCore clocks and clock control signals

Name I/O Source Description
CLK I Clock controller Global clock
MAXCLKLATENCY[2:0] I Implementation-specific static value

Control dynamic clock gating delays. These pins are sampled during reset of the processor.

PERIPHCLK I Clock controller Clock for the timer and Interrupt Controller
PERIPHCLKEN I Clock controller Clock enable for the timer and Interrupt Controller
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